Scalable integer DCT architecture for HEVC encoder

Maher Abdelrasoul; Mohammed S. Sayed; Victor Goulart

doi:10.1109/ISVLSI.2016.98

Scalable integer DCT architecture for HEVC encoder

Maher Abdelrasoul, Mohammed S. Sayed, Victor Goulart

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

HEVC (H.265) standard was proposed as a means to increase the compression rate with no loss in video quality. Large integer DCT, with sizes 16x16 and 32x32, is one of the key new features of the H.265 standard. In this paper, we propose a new scalable architecture for integer DCT in HEVC encoder. The proposed architecture is a fully pipelined architecture with optimized adders bit-widths. It was prototyped on TSMC 65 nm CMOS technology. The prototyping results show the high performance of theproposed architecture. Its gate count is 130K and it can achieve throughput of 9.26 Gsps. The proposed architecture can encode 8K @ 120 fps video sequence with working frequency of 373.25 MHz in real time.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Publisher	IEEE Computer Society
Pages	314-318
Number of pages	5
ISBN (Electronic)	9781467390385
DOIs	https://doi.org/10.1109/ISVLSI.2016.98
Publication status	Published - Sept 2 2016
Event	15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 - Pittsburgh, United States Duration: Jul 11 2016 → Jul 13 2016

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2016-September
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Other

Other	15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Country/Territory	United States
City	Pittsburgh
Period	7/11/16 → 7/13/16

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/ISVLSI.2016.98

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Scalable integer DCT architecture for HEVC encoder. / Abdelrasoul, Maher; Sayed, Mohammed S.; Goulart, Victor.
Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016. IEEE Computer Society, 2016. p. 314-318 7560216 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2016-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abdelrasoul, M, Sayed, MS & Goulart, V 2016, Scalable integer DCT architecture for HEVC encoder. in Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016., 7560216, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2016-September, IEEE Computer Society, pp. 314-318, 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, United States, 7/11/16. https://doi.org/10.1109/ISVLSI.2016.98

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Scalable integer DCT architecture for HEVC encoder

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