Scalable integer DCT architecture for HEVC encoder

Maher Abdelrasoul, Mohammed S. Sayed, Victor Goulart

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    HEVC (H.265) standard was proposed as a means to increase the compression rate with no loss in video quality. Large integer DCT, with sizes 16x16 and 32x32, is one of the key new features of the H.265 standard. In this paper, we propose a new scalable architecture for integer DCT in HEVC encoder. The proposed architecture is a fully pipelined architecture with optimized adders bit-widths. It was prototyped on TSMC 65 nm CMOS technology. The prototyping results show the high performance of theproposed architecture. Its gate count is 130K and it can achieve throughput of 9.26 Gsps. The proposed architecture can encode 8K @ 120 fps video sequence with working frequency of 373.25 MHz in real time.

    Original languageEnglish
    Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
    PublisherIEEE Computer Society
    Pages314-318
    Number of pages5
    ISBN (Electronic)9781467390385
    DOIs
    Publication statusPublished - Sep 2 2016
    Event15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 - Pittsburgh, United States
    Duration: Jul 11 2016Jul 13 2016

    Publication series

    NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
    Volume2016-September
    ISSN (Print)2159-3469
    ISSN (Electronic)2159-3477

    Other

    Other15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
    CountryUnited States
    CityPittsburgh
    Period7/11/167/13/16

    All Science Journal Classification (ASJC) codes

    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

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