TY - JOUR
T1 - Self-aligned gate-all-around InAs/InP core-shell nanowire field-effect transistors
AU - Sasaki, Satoshi
AU - Tateno, Kouta
AU - Zhang, Guoqiang
AU - Pigot, Henry
AU - Harada, Yuichi
AU - Saito, Shiro
AU - Fujiwara, Akira
AU - Sogawa, Tetsuomi
AU - Muraki, Koji
PY - 2015/4/1
Y1 - 2015/4/1
N2 - Field-effect transistors (FETs) are fabricated using an optimized gate-all-around gate-overlap structure and an InAs/InP core-shell nanowire (NW) channel. A short-channel device with the gate length of 100nm exhibits superb on-state properties. Subthreshold swing of 85mV/decade is realized in a long-channel device, suggesting an advantage of the core-shell NW channel. Post-annealing is found to improve the subthreshold properties, which is partly ascribed to the formation of InAlAs alloy at the interface between the InAs core and Al source/drain electrodes.
AB - Field-effect transistors (FETs) are fabricated using an optimized gate-all-around gate-overlap structure and an InAs/InP core-shell nanowire (NW) channel. A short-channel device with the gate length of 100nm exhibits superb on-state properties. Subthreshold swing of 85mV/decade is realized in a long-channel device, suggesting an advantage of the core-shell NW channel. Post-annealing is found to improve the subthreshold properties, which is partly ascribed to the formation of InAlAs alloy at the interface between the InAs core and Al source/drain electrodes.
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U2 - 10.7567/JJAP.54.04DN04
DO - 10.7567/JJAP.54.04DN04
M3 - Article
AN - SCOPUS:84926346234
SN - 0021-4922
VL - 54
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
IS - 4
M1 - 04DN04
ER -