Semantics of a hardware design language for Japanese standardization

Hiroto Yasuura, Nagisa Ishiura

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The authors propose a novel approach to the defining of the formal semantics of a hardware design language (HDL) in the Japanese LSI design language standardization project. The approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, it is possible to describe the vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. The authors introduce a new computation model of hardware behavior called the NES (nondeterministic event sequence) model. The NES model is a very simple model of computation in digital systems and provides an intuitive understanding of the concurrent behavior of HDL description without loss of mathematical strictness.

Original languageEnglish
Pages (from-to)836-839
Number of pages4
JournalProceedings - Design Automation Conference
Publication statusPublished - 1989
Externally publishedYes

Fingerprint

Standardization
Semantics
Hardware
Linguistics
Simulators
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Semantics of a hardware design language for Japanese standardization. / Yasuura, Hiroto; Ishiura, Nagisa.

In: Proceedings - Design Automation Conference, 1989, p. 836-839.

Research output: Contribution to journalArticle

@article{bae9a4d0309944a0b81c7dabd55c3b32,
title = "Semantics of a hardware design language for Japanese standardization",
abstract = "The authors propose a novel approach to the defining of the formal semantics of a hardware design language (HDL) in the Japanese LSI design language standardization project. The approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, it is possible to describe the vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. The authors introduce a new computation model of hardware behavior called the NES (nondeterministic event sequence) model. The NES model is a very simple model of computation in digital systems and provides an intuitive understanding of the concurrent behavior of HDL description without loss of mathematical strictness.",
author = "Hiroto Yasuura and Nagisa Ishiura",
year = "1989",
language = "English",
pages = "836--839",
journal = "Proceedings - Design Automation Conference",
issn = "0738-100X",

}

TY - JOUR

T1 - Semantics of a hardware design language for Japanese standardization

AU - Yasuura, Hiroto

AU - Ishiura, Nagisa

PY - 1989

Y1 - 1989

N2 - The authors propose a novel approach to the defining of the formal semantics of a hardware design language (HDL) in the Japanese LSI design language standardization project. The approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, it is possible to describe the vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. The authors introduce a new computation model of hardware behavior called the NES (nondeterministic event sequence) model. The NES model is a very simple model of computation in digital systems and provides an intuitive understanding of the concurrent behavior of HDL description without loss of mathematical strictness.

AB - The authors propose a novel approach to the defining of the formal semantics of a hardware design language (HDL) in the Japanese LSI design language standardization project. The approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, it is possible to describe the vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. The authors introduce a new computation model of hardware behavior called the NES (nondeterministic event sequence) model. The NES model is a very simple model of computation in digital systems and provides an intuitive understanding of the concurrent behavior of HDL description without loss of mathematical strictness.

UR - http://www.scopus.com/inward/record.url?scp=0024912417&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024912417&partnerID=8YFLogxK

M3 - Article

SP - 836

EP - 839

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

SN - 0738-100X

ER -