Simultaneous optimization of memory configuration and code allocation for low power embedded systems

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

Original languageEnglish
Title of host publicationGLSVLSI 2008
Subtitle of host publicationProceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages403-406
Number of pages4
DOIs
Publication statusPublished - Dec 1 2008
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States
Duration: Mar 4 2008Mar 6 2008

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

OtherGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
CountryUnited States
CityOrlando, FL
Period3/4/083/6/08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Matsumura, T., Ishihara, T., & Yasuura, H. (2008). Simultaneous optimization of memory configuration and code allocation for low power embedded systems. In GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI (pp. 403-406). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1366110.1366206