Simultaneous optimization of memory configuration and code allocation for low power embedded systems

Tadayuki Matsumura; Tohru Ishihara; Hiroto Yasuura

doi:10.1145/1366110.1366206

Simultaneous optimization of memory configuration and code allocation for low power embedded systems

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

Trustee(Vice President)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V _dd and V_th and 2) a static power conscious region which uses high V_dd and V_th. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and V_dd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

Original language	English
Title of host publication	GLSVLSI 2008
Subtitle of host publication	Proceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages	403-406
Number of pages	4
DOIs	https://doi.org/10.1145/1366110.1366206
Publication status	Published - 2008
Event	GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States Duration: Mar 4 2008 → Mar 6 2008

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other	GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
Country/Territory	United States
City	Orlando, FL
Period	3/4/08 → 3/6/08

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1145/1366110.1366206

Cite this

Simultaneous optimization of memory configuration and code allocation for low power embedded systems. / Matsumura, Tadayuki; Ishihara, Tohru; Yasuura, Hiroto.
GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. 2008. p. 403-406 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsumura, T, Ishihara, T & Yasuura, H 2008, Simultaneous optimization of memory configuration and code allocation for low power embedded systems. in GLSVLSI 2008: Proceedings of the 2008 ACM Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 403-406, GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, FL, United States, 3/4/08. https://doi.org/10.1145/1366110.1366206

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abstract = "This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, {\ss}ratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.",

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doi = "10.1145/1366110.1366206",

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series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

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N2 - This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

AB - This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low V dd and Vth and 2) a static power conscious region which uses high Vdd and Vth. This paper also proposes an optimization problem for finding the optimal memory division ratio, the code allocation, ßratio and Vdd so as to minimize the total power consumption of the memory under constraints of static noise margin (SNM), memory access delay and area over-head. Experimental results demonstrate that the total power consumption can be reduced by 50.8% with 7.7% memory array area overhead without degradations of SNM and access delay.

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Simultaneous optimization of memory configuration and code allocation for low power embedded systems

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