Single-cycle-accessible two-level caches and compilation technique for energy reducion

Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

Research output: Contribution to journalArticle

Abstract

A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, at least one extra cycle is needed to access the L1-cache. This degrades the processor performance. Single-cycle-accessible Two-level Cache (STC) architecture proposed in this paper can resolve the problem in the conventional L0-cache based approach. Both a small L0 and a large L1 caches in our STC architecture can be accessed from an MPU core within a single cycle. A compilation technique for effectively utilizing the STC architecture is also presented in this paper. Experiments using several benchmark programs demonstrate that our approach reduces the energy consumption of memory subsystems by 64% in the best case and by 45% on an average without any performance degradation compared to the conventional L0-cache based approach.

Original languageEnglish
Pages (from-to)189-199
Number of pages11
JournalIPSJ Transactions on System LSI Design Methodology
Volume2
DOIs
Publication statusPublished - Dec 1 2009

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Energy utilization
Data storage equipment
Degradation
Experiments

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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Single-cycle-accessible two-level caches and compilation technique for energy reducion. / Yamaguchi, Seiichiro; Ishitobi, Yuriko; Ishihara, Tohru; Yasuura, Hiroto.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 2, 01.12.2009, p. 189-199.

Research output: Contribution to journalArticle

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