TY - GEN
T1 - Single-flux-quantum cache memory architecture
AU - Ishida, Koki
AU - Tanaka, Masamitsu
AU - Ono, Takatsugu
AU - Inoue, Koji
PY - 2016/12/27
Y1 - 2016/12/27
N2 - Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.
AB - Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.
UR - http://www.scopus.com/inward/record.url?scp=85010338108&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85010338108&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2016.7799755
DO - 10.1109/ISOCC.2016.7799755
M3 - Conference contribution
AN - SCOPUS:85010338108
T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
SP - 105
EP - 106
BT - ISOCC 2016 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th International SoC Design Conference, ISOCC 2016
Y2 - 23 October 2016 through 26 October 2016
ER -