Single-flux-quantum cache memory architecture

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages105-106
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - Dec 27 2016
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: Oct 23 2016Oct 26 2016

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other13th International SoC Design Conference, ISOCC 2016
CountryKorea, Republic of
CityJeju
Period10/23/1610/26/16

Fingerprint

Cache memory
Memory architecture
Fluxes
microprocessors
Microprocessor chips
Scalability
logic
prototypes
evaluation

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Ishida, K., Tanaka, M., Ono, T., & Inoue, K. (2016). Single-flux-quantum cache memory architecture. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 105-106). [7799755] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799755

Single-flux-quantum cache memory architecture. / Ishida, Koki; Tanaka, Masamitsu; Ono, Takatsugu; Inoue, Koji.

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 105-106 7799755 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishida, K, Tanaka, M, Ono, T & Inoue, K 2016, Single-flux-quantum cache memory architecture. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799755, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 10/23/16. https://doi.org/10.1109/ISOCC.2016.7799755
Ishida K, Tanaka M, Ono T, Inoue K. Single-flux-quantum cache memory architecture. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 105-106. 7799755. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). https://doi.org/10.1109/ISOCC.2016.7799755
Ishida, Koki ; Tanaka, Masamitsu ; Ono, Takatsugu ; Inoue, Koji. / Single-flux-quantum cache memory architecture. ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 105-106 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).
@inproceedings{d348e3f3e92644ea8b4f083cd95b7b91,
title = "Single-flux-quantum cache memory architecture",
abstract = "Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.",
author = "Koki Ishida and Masamitsu Tanaka and Takatsugu Ono and Koji Inoue",
year = "2016",
month = "12",
day = "27",
doi = "10.1109/ISOCC.2016.7799755",
language = "English",
series = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "105--106",
booktitle = "ISOCC 2016 - International SoC Design Conference",
address = "United States",

}

TY - GEN

T1 - Single-flux-quantum cache memory architecture

AU - Ishida, Koki

AU - Tanaka, Masamitsu

AU - Ono, Takatsugu

AU - Inoue, Koji

PY - 2016/12/27

Y1 - 2016/12/27

N2 - Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.

AB - Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-lowpower natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: A large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-Arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.

UR - http://www.scopus.com/inward/record.url?scp=85010338108&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85010338108&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2016.7799755

DO - 10.1109/ISOCC.2016.7799755

M3 - Conference contribution

AN - SCOPUS:85010338108

T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

SP - 105

EP - 106

BT - ISOCC 2016 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

ER -