Abstract
A unate gate is a logical gate computing a unate Boolean function, which is monotone in each variable. Examples of unate gates are AND gates, OR gates, NOT gates, threshold gates, etc. A unate circuit C is a combinatorial logic circuit consisting of unate gates. Let f be a symmetric Boolean function of n variables, such as the Parity function, MOD function, and Majority function. Let m0 and m1 be the maximum numbers of consecutive 0's and consecutive 1's in the value vector of f, respectively, and let l=minm0,m1 and m=maxm0,m1. Let C be a unate circuit computing f. Let s be the size of the circuit C, that is, C consists of s unate gates. Let e be the energy of C, that is, e is the maximum number of gates outputting "1" over all inputs to C. In this paper, we show that there is a tradeoff between the size s and the energy e of C. More precisely, we show that (n+1-l)m≤se. We also present lower bounds on the size s of C represented in terms of n, l and m. Our tradeoff immediately implies that logn≤elogs for every unate circuit C computing the Parity function of n variables.
| Original language | English |
|---|---|
| Pages (from-to) | 773-782 |
| Number of pages | 10 |
| Journal | Theoretical Computer Science |
| Volume | 412 |
| Issue number | 8-10 |
| DOIs | |
| Publication status | Published - Mar 4 2011 |
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All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)
Cite this
Sizeenergy tradeoffs for unate circuits computing symmetric Boolean functions. / Uchizawa, Kei; Takimoto, Eiji; Nishizeki, Takao.
In: Theoretical Computer Science, Vol. 412, No. 8-10, 04.03.2011, p. 773-782.Research output: Contribution to journal › Article
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TY - JOUR
T1 - Sizeenergy tradeoffs for unate circuits computing symmetric Boolean functions
AU - Uchizawa, Kei
AU - Takimoto, Eiji
AU - Nishizeki, Takao
PY - 2011/3/4
Y1 - 2011/3/4
N2 - A unate gate is a logical gate computing a unate Boolean function, which is monotone in each variable. Examples of unate gates are AND gates, OR gates, NOT gates, threshold gates, etc. A unate circuit C is a combinatorial logic circuit consisting of unate gates. Let f be a symmetric Boolean function of n variables, such as the Parity function, MOD function, and Majority function. Let m0 and m1 be the maximum numbers of consecutive 0's and consecutive 1's in the value vector of f, respectively, and let l=minm0,m1 and m=maxm0,m1. Let C be a unate circuit computing f. Let s be the size of the circuit C, that is, C consists of s unate gates. Let e be the energy of C, that is, e is the maximum number of gates outputting "1" over all inputs to C. In this paper, we show that there is a tradeoff between the size s and the energy e of C. More precisely, we show that (n+1-l)m≤se. We also present lower bounds on the size s of C represented in terms of n, l and m. Our tradeoff immediately implies that logn≤elogs for every unate circuit C computing the Parity function of n variables.
AB - A unate gate is a logical gate computing a unate Boolean function, which is monotone in each variable. Examples of unate gates are AND gates, OR gates, NOT gates, threshold gates, etc. A unate circuit C is a combinatorial logic circuit consisting of unate gates. Let f be a symmetric Boolean function of n variables, such as the Parity function, MOD function, and Majority function. Let m0 and m1 be the maximum numbers of consecutive 0's and consecutive 1's in the value vector of f, respectively, and let l=minm0,m1 and m=maxm0,m1. Let C be a unate circuit computing f. Let s be the size of the circuit C, that is, C consists of s unate gates. Let e be the energy of C, that is, e is the maximum number of gates outputting "1" over all inputs to C. In this paper, we show that there is a tradeoff between the size s and the energy e of C. More precisely, we show that (n+1-l)m≤se. We also present lower bounds on the size s of C represented in terms of n, l and m. Our tradeoff immediately implies that logn≤elogs for every unate circuit C computing the Parity function of n variables.
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UR - http://www.scopus.com/inward/citedby.url?scp=79151486492&partnerID=8YFLogxK
U2 - 10.1016/j.tcs.2010.11.022
DO - 10.1016/j.tcs.2010.11.022
M3 - Article
AN - SCOPUS:79151486492
VL - 412
SP - 773
EP - 782
JO - Theoretical Computer Science
JF - Theoretical Computer Science
SN - 0304-3975
IS - 8-10
ER -