Solving satisfiability problems on FPGAs

This paper presents a report on a new approach for solving satisfiability problems (SAT), i.e., creating a specialized logic circuit to solve each problem instance on Field Programmable Gate Arrays (FP-GAs). Recently, due to advances in FPGA technologies, users can now create their own reconfigurable logic circuits. Furthermore, by using current automatic logic synthesis technologies, users are able to design logic circuits automatically using a high level hardware description language (HDL). The combination of these two technologies have enabled users to rapidly create logic circuits specialized for solving individual problem instances. Satisfiability problems (SAT) were chosen because they make up an important subclass of NP-hard problems. We have developed a new algorithm called parallel-checking, which is suitable for this approach. In the algorithm, all variable values are assigned simultaneously, and all constraints are checked concurrently. Simulation results show that the order of the search tree size in this algorithm is approximately the same as that in the Davis-Putnam procedure. Then, we show how the parallel-checking algorithm can be implemented on FPGAs.