Source/drain junction fabrication for Ge metal-oxide-semiconductor field-effect transistors

Keisuke Yamamoto, Takeshi Yamanaka, Ryuji Ueno, Kana Hirayama, Haigui Yang, Dong Wang, Hiroshi Nakashima

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

We established fabrication methods for high-quality Ge n +/p and p +/n junctions using thermal diffusion of P and implantation of B, respectively. The carrier concentrations in n + and p + layers were as high as 4 × 10 19 and 2 × 10 19 cm - 3, respectively. It was found that a peripheral surface-state current dominates the reverse leakage current in an n +/p junction diode. The protection of junction surfaces from plasma damage during the SiO 2 deposition was essential to achieve high-quality source/drain junctions. The surface passivation with a GeO 2 interlayer was harmful to an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) because of an increase in a surface leakage current due to inversion carriers. For a p-channel MOSFET, on the other hand, the GeO 2 interlayer plays a role in decreasing the surface leakage current.

Original languageEnglish
Pages (from-to)3382-3386
Number of pages5
JournalThin Solid Films
Volume520
Issue number8
DOIs
Publication statusPublished - Feb 1 2012

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films
  • Metals and Alloys
  • Materials Chemistry

Cite this