Stable Hysteresis-Free MoS2Transistors with Low-k/High-k Bilayer Gate Dielectrics

Zhijie Zhang, Meng Su, Guoli Li, Jianlu Wang, Xiaoyu Zhang, Johnny C. Ho, Chunlan Wang, Da Wan, Xingqiang Liu, Lei Liao

Research output: Contribution to journalArticlepeer-review

Abstract

Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high-k property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to 7.0 × 1011 cm-2 C eV-1 and -2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.

Original languageEnglish
Article number9109258
Pages (from-to)1036-1039
Number of pages4
JournalIEEE Electron Device Letters
Volume41
Issue number7
DOIs
Publication statusPublished - Jul 2020
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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