The inevitable fluctuation in fabrication processes results in LSI chips with various critical path delay even though all the chips are fabricated from the same design. Therefore, in LSI design, it is important to estimate what percentage of the fabricated chips will achieve the performance level and to maximize the percentage. This paper presents a model and a method to analyze statistical delay of RT-level data path designs. The method predicts the probability that the fabricated circuits will work at a user specified clock period. Using the method, we can estimate a tight bound on the worst case critical path delay of the circuits. Based on the delay analysis method, a high-level module binding algorithm which maximizes the probability is also proposed. Experimental results demonstrate that the proposed statistical delay analysis method leads to lower cost or higher-performance designs than conventional delay analysis methods.