Study of Laser Ablation Slits in Stress Reduced Embedded Die Substrate Fabricated for Heterogeneous Integration

Masamitsu Matsuura, Tanemasa Asano, Haruichi Kanaya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The residual stress of the silicon die in an embedded die substrate was investigated. A silicon test element chip having piezo-resistance gauges was embedded in a printed circuit board substrate with the newly developed hollow chamber and laser-drilled slits around die technology. The embedded die was mechanically held with a copper redistribution layer (RDL), and dielectric epoxy resin remained at a part of the periphery. Slits of various designs were fabricated. The residual stresses near the center and a corner of the chip and their change with temperature were measured. The laser slits enabled to reduce the residual stress due to the difference in coefficient of thermal expansion (CTE) between materials.

Original languageEnglish
Title of host publication2021 IEEE 23rd Electronics Packaging Technology Conference, EPTC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages563-567
Number of pages5
ISBN (Electronic)9781665416191
DOIs
Publication statusPublished - 2021
Event23rd IEEE Electronics Packaging Technology Conference, EPTC 2021 - Virtual, Online, Singapore
Duration: Dec 1 2021Dec 30 2021

Publication series

Name2021 IEEE 23rd Electronics Packaging Technology Conference, EPTC 2021

Conference

Conference23rd IEEE Electronics Packaging Technology Conference, EPTC 2021
Country/TerritorySingapore
CityVirtual, Online
Period12/1/2112/30/21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Fluid Flow and Transfer Processes

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