TY - GEN
T1 - Study of Laser Ablation Slits in Stress Reduced Embedded Die Substrate Fabricated for Heterogeneous Integration
AU - Matsuura, Masamitsu
AU - Asano, Tanemasa
AU - Kanaya, Haruichi
N1 - Funding Information:
This work was partially supported by the Cabinet Office (CAO), Cross-ministerial Strategic Innovation Promotion Program (SIP), A“ n intelligent knowledge processing infrastructure, integrating physical and virtual domains” (NEDO) (JPNP18014), SCOPE (JP19501002), and KAKENHI(JP21K04177) JSPS.
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - The residual stress of the silicon die in an embedded die substrate was investigated. A silicon test element chip having piezo-resistance gauges was embedded in a printed circuit board substrate with the newly developed hollow chamber and laser-drilled slits around die technology. The embedded die was mechanically held with a copper redistribution layer (RDL), and dielectric epoxy resin remained at a part of the periphery. Slits of various designs were fabricated. The residual stresses near the center and a corner of the chip and their change with temperature were measured. The laser slits enabled to reduce the residual stress due to the difference in coefficient of thermal expansion (CTE) between materials.
AB - The residual stress of the silicon die in an embedded die substrate was investigated. A silicon test element chip having piezo-resistance gauges was embedded in a printed circuit board substrate with the newly developed hollow chamber and laser-drilled slits around die technology. The embedded die was mechanically held with a copper redistribution layer (RDL), and dielectric epoxy resin remained at a part of the periphery. Slits of various designs were fabricated. The residual stresses near the center and a corner of the chip and their change with temperature were measured. The laser slits enabled to reduce the residual stress due to the difference in coefficient of thermal expansion (CTE) between materials.
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U2 - 10.1109/EPTC53413.2021.9663982
DO - 10.1109/EPTC53413.2021.9663982
M3 - Conference contribution
AN - SCOPUS:85124805577
T3 - 2021 IEEE 23rd Electronics Packaging Technology Conference, EPTC 2021
SP - 563
EP - 567
BT - 2021 IEEE 23rd Electronics Packaging Technology Conference, EPTC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd IEEE Electronics Packaging Technology Conference, EPTC 2021
Y2 - 1 December 2021 through 30 December 2021
ER -