Chemical-mechanical polishing (CMP) has been widely accepted for the planarization of multi-layer structures in semiconductor manufacturing. High performance CMP for the planarization of přemetal and inter layer dielectrics is strongly required. Conventional CMP process using the stack-type pads shows good within-wafer uniformity. However this process produces degradation in planarity, especially between center and edge areas of logic devices. In this work, we described an approach to the optimized dielectric planarization method using the hard-pad-based CMP process and achieve improved wafer-scaled uniformity and within-die planarity, simultaneously. By optimizing both polishing conditions and the consumables of the polishers, the hard pad-based process showed an at least 1.6-time improvement in step height reduction compared to the stack-type pad process and a comparable within-wafer uniformity.
|Number of pages||5|
|Journal||Seimitsu Kogaku Kaishi/Journal of the Japan Society for Precision Engineering|
|Publication status||Published - Nov 2008|
All Science Journal Classification (ASJC) codes
- Mechanical Engineering