Suppressing plasma induced degradation of gate oxide using silicon-on-insulator structures

Kiyoshi Arita, Masashi Akamatsu, Tanemasa Asano

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1 Citation (Scopus)

Abstract

Plasma-process induced degradation of gate oxide of metal/oxide/silicon (MOS) devices on silicon-on-insulator (SOI) structures and bulk wafers was investigated. In order to evaluate the degradation of the gate oxide, the charge-to-breakdown Qbd of the MOS capacitors was measured under a constant current condition. It was found that the degradation of the gate oxide could be drastically suppressed using SOI. A thicker buried oxide layer showed greater suppression of the gate oxide degradation. A smaller device island size showed lower gate oxide degradation, although the dependence was rather weak. An electrical model is discussed, to account for the effect of SOI, in which the capacitance of the buried oxide played a key role in suppressing the degradation.

Original languageEnglish
Pages (from-to)1278-1281
Number of pages4
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume37
Issue number3 SUPPL. B
DOIs
Publication statusPublished - Mar 1998
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

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