Suppression of dynamic on-resistance increase and gate charge measurements in high-voltage GaN-HEMTs with optimized field-plate structure

Wataru Saito, Tomohiro Nitta, Yorito Kakiuchi, Yasunobu Saito, Kunio Tsuda, Ichiro Omura, Masakazu Yamaguchi

Research output: Contribution to journalArticlepeer-review

155 Citations (Scopus)

Abstract

The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Qgd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Qgd/A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, RONA was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, RONQgd for 600-V device was reduced to 0.32 ΩnC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.

Original languageEnglish
Pages (from-to)1825-1830
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume54
Issue number8
DOIs
Publication statusPublished - Aug 1 2007
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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