Abstract
The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generator. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesize parallel index generators. Experimental results show the proposed method outperforms other existing methods. Also, A novel architecture of index generator which is suitable for parallelized implementation is introduced. A new architecture has advantages in the sense of both area and delay.
| Original language | English |
|---|---|
| Pages (from-to) | 2451-2458 |
| Number of pages | 8 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E97A |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - Dec 1 2014 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Electrical and Electronic Engineering
Cite this
Synthesis algorithm for parallel index generator. / Matsunaga, Yusuke.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97A, No. 12, 01.12.2014, p. 2451-2458.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Synthesis algorithm for parallel index generator
AU - Matsunaga, Yusuke
PY - 2014/12/1
Y1 - 2014/12/1
N2 - The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generator. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesize parallel index generators. Experimental results show the proposed method outperforms other existing methods. Also, A novel architecture of index generator which is suitable for parallelized implementation is introduced. A new architecture has advantages in the sense of both area and delay.
AB - The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generator. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesize parallel index generators. Experimental results show the proposed method outperforms other existing methods. Also, A novel architecture of index generator which is suitable for parallelized implementation is introduced. A new architecture has advantages in the sense of both area and delay.
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U2 - 10.1587/transfun.E97.A.2451
DO - 10.1587/transfun.E97.A.2451
M3 - Article
AN - SCOPUS:84924546628
VL - E97A
SP - 2451
EP - 2458
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -