Synthesis algorithm for parallel index generator

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generator. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesize parallel index generators. Experimental results show the proposed method outperforms other existing methods. Also, A novel architecture of index generator which is suitable for parallelized implementation is introduced. A new architecture has advantages in the sense of both area and delay.

Original languageEnglish
Pages (from-to)2451-2458
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE97A
Issue number12
DOIs
Publication statusPublished - Dec 1 2014

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Generator
Synthesis
Multi-valued Logic
Hardware
Latency
Partitioning
Efficient Algorithms
Experimental Results
Architecture

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Electrical and Electronic Engineering

Cite this

Synthesis algorithm for parallel index generator. / Matsunaga, Yusuke.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97A, No. 12, 01.12.2014, p. 2451-2458.

Research output: Contribution to journalArticle

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