Synthesis algorithm of parallel index generation units

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The index generation function is a multi-valued logic function which checks if the given input vector is a registered or not, and returns its index value if the vector is registered. If the latency of the operation is critical, dedicated hardware is used for implementing the index generation functions. This paper proposes a method implementing the index generation functions using parallel index generation units. A novel and efficient algorithm called 'conflict free partitioning' is proposed to synthesis parallel index generation units. Experimental results show the proposed method outperforms other existing methods.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9783981537024
DOIs
Publication statusPublished - 2014
Event17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
Duration: Mar 24 2014Mar 28 2014

Other

Other17th Design, Automation and Test in Europe, DATE 2014
CountryGermany
CityDresden
Period3/24/143/28/14

Fingerprint

Hardware

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Matsunaga, Y. (2014). Synthesis algorithm of parallel index generation units. In Proceedings - Design, Automation and Test in Europe, DATE 2014 [6800511] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/DATE2014.310

Synthesis algorithm of parallel index generation units. / Matsunaga, Yusuke.

Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6800511.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsunaga, Y 2014, Synthesis algorithm of parallel index generation units. in Proceedings - Design, Automation and Test in Europe, DATE 2014., 6800511, Institute of Electrical and Electronics Engineers Inc., 17th Design, Automation and Test in Europe, DATE 2014, Dresden, Germany, 3/24/14. https://doi.org/10.7873/DATE2014.310
Matsunaga Y. Synthesis algorithm of parallel index generation units. In Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6800511 https://doi.org/10.7873/DATE2014.310
Matsunaga, Yusuke. / Synthesis algorithm of parallel index generation units. Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 2014.
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