Synthesis of minimum-cost multilevel logic networks via genetic algorithm

Barry Shackleford, Etsuko Okushi, Mitsuliiro Yasuda, Hisao Koizuml, Katsuhiko Seo, Hiroto Yasuura

Research output: Contribution to journalArticle

Abstract

The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (DCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.

Original languageEnglish
Pages (from-to)2528-2536
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE83-A
Issue number12
Publication statusPublished - Jan 1 2000
Externally publishedYes

Fingerprint

Network Algorithms
Genetic algorithms
Genetic Algorithm
Synthesis
Logic
Costs
Logic Synthesis
Cost functions
Parity
Accelerate
System Design
Cost Function
Odd
Systems analysis
Hardware
Networks (circuits)
Cell
Design

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Synthesis of minimum-cost multilevel logic networks via genetic algorithm. / Shackleford, Barry; Okushi, Etsuko; Yasuda, Mitsuliiro; Koizuml, Hisao; Seo, Katsuhiko; Yasuura, Hiroto.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E83-A, No. 12, 01.01.2000, p. 2528-2536.

Research output: Contribution to journalArticle

Shackleford, Barry ; Okushi, Etsuko ; Yasuda, Mitsuliiro ; Koizuml, Hisao ; Seo, Katsuhiko ; Yasuura, Hiroto. / Synthesis of minimum-cost multilevel logic networks via genetic algorithm. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2000 ; Vol. E83-A, No. 12. pp. 2528-2536.
@article{b13aaff3cdfa4743aeb8d90e7951e88c,
title = "Synthesis of minimum-cost multilevel logic networks via genetic algorithm",
abstract = "The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (DCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.",
author = "Barry Shackleford and Etsuko Okushi and Mitsuliiro Yasuda and Hisao Koizuml and Katsuhiko Seo and Hiroto Yasuura",
year = "2000",
month = "1",
day = "1",
language = "English",
volume = "E83-A",
pages = "2528--2536",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Synthesis of minimum-cost multilevel logic networks via genetic algorithm

AU - Shackleford, Barry

AU - Okushi, Etsuko

AU - Yasuda, Mitsuliiro

AU - Koizuml, Hisao

AU - Seo, Katsuhiko

AU - Yasuura, Hiroto

PY - 2000/1/1

Y1 - 2000/1/1

N2 - The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (DCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.

AB - The problem of synthesizing a minimum-cost logic network is formulated for a genetic algorithm (GA). When benchmarked against a commercial logic synthesis tool, an odd parity circuit required 24 basic cells (DCs) versus 28 BCs for the design produced by the commercial system. A magnitude comparator required 20 BCs versus 21 BCs for the commercial system's design. Poor temporal performance, however, is the main disadvantage of the GA-based approach. The design of a hardware-based cost function that would accelerate the GA by several thousand times is described.

UR - http://www.scopus.com/inward/record.url?scp=0034504253&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034504253&partnerID=8YFLogxK

M3 - Article

VL - E83-A

SP - 2528

EP - 2536

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -