Synthesis of parallel prefix adders considering switching activities

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper addresses parallel prefix adder synthesis which targets minimization of the total switching activities under bitwise timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders at technology-independent level. An approach for timing-driven area minimization has been proposed which first finds the exact minimum solution on a specific subset of prefix graphs by dynamic programming, then restructures the result for further reduction by removing restriction on the subset. This approach can be applied for switching cost minimization almost directly, though it is not so effective as area minimization in some cases. In this paper, a heuristic is proposed which estimates the effect of the restructuring phase and improve cost calculation fo some specific cases. Through various kinds of experiments, conditions where this approach can be executed effectively is also discussed. & copy; 2008 IEEE.

Original languageEnglish
Title of host publication26th IEEE International Conference on Computer Design 2008, ICCD
Pages404-409
Number of pages6
DOIs
Publication statusPublished - Dec 1 2008
Event26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States
Duration: Oct 12 2008Oct 15 2008

Publication series

Name26th IEEE International Conference on Computer Design 2008, ICCD

Other

Other26th IEEE International Conference on Computer Design 2008, ICCD
CountryUnited States
CityLake Tahoe, CA
Period10/12/0810/15/08

Fingerprint

Adders
Thermodynamic properties
Dynamic programming
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Matsunaga, T., Kimura, S., & Matsunaga, Y. (2008). Synthesis of parallel prefix adders considering switching activities. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 404-409). [4751892] (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751892

Synthesis of parallel prefix adders considering switching activities. / Matsunaga, Taeko; Kimura, Shinji; Matsunaga, Yusuke.

26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 404-409 4751892 (26th IEEE International Conference on Computer Design 2008, ICCD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsunaga, T, Kimura, S & Matsunaga, Y 2008, Synthesis of parallel prefix adders considering switching activities. in 26th IEEE International Conference on Computer Design 2008, ICCD., 4751892, 26th IEEE International Conference on Computer Design 2008, ICCD, pp. 404-409, 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, United States, 10/12/08. https://doi.org/10.1109/ICCD.2008.4751892
Matsunaga T, Kimura S, Matsunaga Y. Synthesis of parallel prefix adders considering switching activities. In 26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 404-409. 4751892. (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751892
Matsunaga, Taeko ; Kimura, Shinji ; Matsunaga, Yusuke. / Synthesis of parallel prefix adders considering switching activities. 26th IEEE International Conference on Computer Design 2008, ICCD. 2008. pp. 404-409 (26th IEEE International Conference on Computer Design 2008, ICCD).
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