System LSI design methods for low power LSIs

Hiroto Yasuura, Tohru Ishihara

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

Original languageEnglish
Pages (from-to)143-152
Number of pages10
JournalIEICE Transactions on Electronics
VolumeE83-C
Issue number2
Publication statusPublished - Jan 1 2000

Fingerprint

Systems analysis

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

System LSI design methods for low power LSIs. / Yasuura, Hiroto; Ishihara, Tohru.

In: IEICE Transactions on Electronics, Vol. E83-C, No. 2, 01.01.2000, p. 143-152.

Research output: Contribution to journalArticle

Yasuura, H & Ishihara, T 2000, 'System LSI design methods for low power LSIs', IEICE Transactions on Electronics, vol. E83-C, no. 2, pp. 143-152.
Yasuura, Hiroto ; Ishihara, Tohru. / System LSI design methods for low power LSIs. In: IEICE Transactions on Electronics. 2000 ; Vol. E83-C, No. 2. pp. 143-152.
@article{943afece67674b73a784003ad07d2557,
title = "System LSI design methods for low power LSIs",
abstract = "Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.",
author = "Hiroto Yasuura and Tohru Ishihara",
year = "2000",
month = "1",
day = "1",
language = "English",
volume = "E83-C",
pages = "143--152",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "2",

}

TY - JOUR

T1 - System LSI design methods for low power LSIs

AU - Yasuura, Hiroto

AU - Ishihara, Tohru

PY - 2000/1/1

Y1 - 2000/1/1

N2 - Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

AB - Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

UR - http://www.scopus.com/inward/record.url?scp=0033885875&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033885875&partnerID=8YFLogxK

M3 - Article

VL - E83-C

SP - 143

EP - 152

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 2

ER -