Test architecture optimization for system-on-a-chip under floorplanning constraints

Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga

Research output: Contribution to journalArticle

Abstract

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

Original languageEnglish
Pages (from-to)3174-3184
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE87-A
Issue number12
Publication statusPublished - Jan 1 2004

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Floorplanning
Chip
Optimization
Locality
Wire
Architecture
Model

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Test architecture optimization for system-on-a-chip under floorplanning constraints. / Sugihara, Makoto; Murakami, Kazuaki; Matsunaga, Yusuke.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 12, 01.01.2004, p. 3174-3184.

Research output: Contribution to journalArticle

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