Abstract
In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.
| Original language | English |
|---|---|
| Pages (from-to) | 3174-3184 |
| Number of pages | 11 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E87-A |
| Issue number | 12 |
| Publication status | Published - Jan 1 2004 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
Test architecture optimization for system-on-a-chip under floorplanning constraints. / Sugihara, Makoto; Murakami, Kazuaki; Matsunaga, Yusuke.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 12, 01.01.2004, p. 3174-3184.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Test architecture optimization for system-on-a-chip under floorplanning constraints
AU - Sugihara, Makoto
AU - Murakami, Kazuaki
AU - Matsunaga, Yusuke
PY - 2004/1/1
Y1 - 2004/1/1
N2 - In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.
AB - In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.
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UR - http://www.scopus.com/inward/citedby.url?scp=11144324291&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:11144324291
VL - E87-A
SP - 3174
EP - 3184
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -