The Effect of Parallel-Connected Varistor on UIS Robustness of SiC MOSFETs for Solid-State Circuit Breakers Application

Zaiqi Lou, Yunjie Zhu, Shinichi Nishizawa, Wataru Saito

Research output: Contribution to journalConference articlepeer-review

Abstract

This paper aims to clarify the effect of parallel-connected varistor on unclamped inductive switching (UIS) robustness of SiC MOSFETs to improve the cut-off current capability of solid-state circuit breakers (SSCB). Because the operation of UIS tests is similar to that in the interruption of SSCB, UIS tests of SiC MOSFETs without varistor and with a parallel-connected varistor were implemented. It was found that the cut-off current of SiC MOSFETs with the varistor is much larger than that of SiC MOSFETs without varistor. The effect of varistor on increase of cut-off current depends on the MOS-gate type. The cut-off current is 3-5 times higher for planar-gate devices and 5-10 times higher for trench-gate devices compared with no varistor condition. To analyze mechanism of cut-off current increased by the varistor, the junction temperature in UIS tests with and without the varistor was estimated by simulation using experimental wave-forms. The simulation results show that the destruction mechanism of SiC MOSFETs is changed by varistor connection due to change of self-heating timing during the UIS.

Original languageEnglish
Pages (from-to)175-179
Number of pages5
JournalETG-Fachbericht
Volume2022-March
Issue number165
Publication statusPublished - 2022
Event12th International Conference on Integrated Power Electronics Systems, CIPS 2022 - Berlin, Germany
Duration: Mar 15 2022Mar 17 2022

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Energy Engineering and Power Technology

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