The effect of temperature on cache size tuning for low energy embedded systems

Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in these systems. In older technology nodes, active power was the primary contributor to total power dissipation of a CMOS design. However, with the scaling of feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Temperature is a factor which exponentially increases the leakage current. In this paper, we show the effects of temperature on the selection of optimal cache size for low energy embedded systems. Our results show that for a given application, the optimal cache size selection is affected by the temperature. Our experiments have been done for 100nm technology. Our study reveals that the cache size selection for different temperatures depends on the rate at which cache miss increases when reducing the cache size. When the miss rate increases sharply the optimal point is the same for all examined temperatures, however when it becomes smoother, the optimal point for different temperatures begin to get farther.

Original languageEnglish
Title of host publicationGLSVLSI'07
Subtitle of host publicationProceedings of the 2007 ACM Great Lakes Symposium on VLSI
Pages453-456
Number of pages4
DOIs
Publication statusPublished - 2007
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
Duration: Mar 11 2007Mar 13 2007

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other17th Great Lakes Symposium on VLSI, GLSVLSI'07
CountryItaly
CityStresa-Lago Maggiore
Period3/11/073/13/07

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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