TY - GEN
T1 - The Kyushu University reconfigurable parallel processor - Design of memory and intercommunication architectures
AU - Murakami, Kazuaki
AU - Mori, Shin Ichiro
AU - Fukuda, Akira
AU - Sueyoshi, Toshinori
AU - Tomita, Shinji
PY - 1989/6/1
Y1 - 1989/6/1
N2 - The reconfigurable parallel processor system under development at Kyushu University is an MIMD-type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S NXNcrossbar networks (currently S is 1). Each PE (Processing Element) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set, an MMU (Memory Management Unit) with 64K bytes of cache, 4M bytes of memory, and an MCU (Message Communication Unit). The modular 128×128 crossbar network is implemented by arranging 256 identical 8×8 crossbar LSI-modules in a 16 × 16 matrix form. The full 128-PE configuration achieves supercomputer levels of performance by providing 1.28 GIPS and 205 MFLOPS of computing power, 512M bytes of memory, and 2.56G bytes/s of inter-PE communication bandwidth. At the same time, it exploits unique reconfigurability in the memory and intercommunication architectures. By utilizing these two types of reconfigurability, we believe that the system can be effectively tailored to a wide spectrum of applications such as numerical computation, image processing, computer graphics, artificial intelligence, neurocomputing, and so on.
AB - The reconfigurable parallel processor system under development at Kyushu University is an MIMD-type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S NXNcrossbar networks (currently S is 1). Each PE (Processing Element) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set, an MMU (Memory Management Unit) with 64K bytes of cache, 4M bytes of memory, and an MCU (Message Communication Unit). The modular 128×128 crossbar network is implemented by arranging 256 identical 8×8 crossbar LSI-modules in a 16 × 16 matrix form. The full 128-PE configuration achieves supercomputer levels of performance by providing 1.28 GIPS and 205 MFLOPS of computing power, 512M bytes of memory, and 2.56G bytes/s of inter-PE communication bandwidth. At the same time, it exploits unique reconfigurability in the memory and intercommunication architectures. By utilizing these two types of reconfigurability, we believe that the system can be effectively tailored to a wide spectrum of applications such as numerical computation, image processing, computer graphics, artificial intelligence, neurocomputing, and so on.
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U2 - 10.1145/318789.318828
DO - 10.1145/318789.318828
M3 - Conference contribution
AN - SCOPUS:84944291017
T3 - Proceedings of the International Conference on Supercomputing
SP - 351
EP - 360
BT - Proceedings of the 3rd International Conference on Supercomputing, ICS 1989
PB - Association for Computing Machinery
T2 - 3rd International Conference on Supercomputing, ICS 1989
Y2 - 5 June 1989 through 9 June 1989
ER -