### Abstract

We propose a new parallel sorting scheme, called the parallel enumeration sorting scheme, which is suitable for VLSI implementation. This scheme can be introduced to conventional computer systems without changing their architecture. In this scheme, sorting is divided into two stages, the ordering process and the rearranging one. The latter can be efficiently performed by central processing units or intelligent memory devices. For implementations of the ordering process by VLSI technology, we design a new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting. Data are serially transmitted between the sorting circuit and memory devices and the total communication between them is minimized. The basic structure used in the algorithm is called a bus connected cellular array structure with pipeline and parallel processing. The circuit consists of a linear array of one type of simple cell and two buses connecting all cells for efficient global communications in the circuit. The sorting circuit is simple, regular and small enough for realization by today's VLSI technology. We discuss several applications of the sorting circuit and evaluate its performance.

Original language | English |
---|---|

Pages (from-to) | 1192-1201 |

Number of pages | 10 |

Journal | IEEE Transactions on Computers |

Volume | C-31 |

Issue number | 12 |

DOIs | |

Publication status | Published - Jan 1 1982 |

Externally published | Yes |

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### All Science Journal Classification (ASJC) codes

- Theoretical Computer Science
- Software
- Hardware and Architecture
- Computational Theory and Mathematics

### Cite this

*IEEE Transactions on Computers*,

*C-31*(12), 1192-1201. https://doi.org/10.1109/TC.1982.1675943

**The Parallel Enumeration Sorting Scheme for VLSI.** / Yasuura, Hiroto; Takagi, Naofumi; Yajima, Shuzo.

Research output: Contribution to journal › Article

*IEEE Transactions on Computers*, vol. C-31, no. 12, pp. 1192-1201. https://doi.org/10.1109/TC.1982.1675943

}

TY - JOUR

T1 - The Parallel Enumeration Sorting Scheme for VLSI

AU - Yasuura, Hiroto

AU - Takagi, Naofumi

AU - Yajima, Shuzo

PY - 1982/1/1

Y1 - 1982/1/1

N2 - We propose a new parallel sorting scheme, called the parallel enumeration sorting scheme, which is suitable for VLSI implementation. This scheme can be introduced to conventional computer systems without changing their architecture. In this scheme, sorting is divided into two stages, the ordering process and the rearranging one. The latter can be efficiently performed by central processing units or intelligent memory devices. For implementations of the ordering process by VLSI technology, we design a new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting. Data are serially transmitted between the sorting circuit and memory devices and the total communication between them is minimized. The basic structure used in the algorithm is called a bus connected cellular array structure with pipeline and parallel processing. The circuit consists of a linear array of one type of simple cell and two buses connecting all cells for efficient global communications in the circuit. The sorting circuit is simple, regular and small enough for realization by today's VLSI technology. We discuss several applications of the sorting circuit and evaluate its performance.

AB - We propose a new parallel sorting scheme, called the parallel enumeration sorting scheme, which is suitable for VLSI implementation. This scheme can be introduced to conventional computer systems without changing their architecture. In this scheme, sorting is divided into two stages, the ordering process and the rearranging one. The latter can be efficiently performed by central processing units or intelligent memory devices. For implementations of the ordering process by VLSI technology, we design a new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting. Data are serially transmitted between the sorting circuit and memory devices and the total communication between them is minimized. The basic structure used in the algorithm is called a bus connected cellular array structure with pipeline and parallel processing. The circuit consists of a linear array of one type of simple cell and two buses connecting all cells for efficient global communications in the circuit. The sorting circuit is simple, regular and small enough for realization by today's VLSI technology. We discuss several applications of the sorting circuit and evaluate its performance.

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U2 - 10.1109/TC.1982.1675943

DO - 10.1109/TC.1982.1675943

M3 - Article

AN - SCOPUS:0020312595

VL - C-31

SP - 1192

EP - 1201

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 12

ER -