TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION.

Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A new high-speed gate-level logic simulation algorithm, called Time First Evaluation Algorithm (T-algorithm), is proposed. In this algorithm, the simulation proceeds as time progresses in the simulated circuit, and events are evaluated and propagated in order of their occurrence. The principal idea is, that all events that have already occurred can be evaluated for each gate independently of other gates. All events on a gate that it has been possible to evaluate are processed at once; thus, the simulation advances asynchronously in each gate of the simulated circuit.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages197-199
Number of pages3
Publication statusPublished - 1984
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Ishiura, N., Yasuura, H., & Yajima, S. (1984). TIME FIRST EVALUATION ALGORITHM FOR HIGH-SPEED LOGIC SIMULATION. In Unknown Host Publication Title (pp. 197-199). IEEE.