Abstract
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.
| Original language | English |
|---|---|
| Pages (from-to) | 359-369 |
| Number of pages | 11 |
| Journal | IEICE Transactions on Electronics |
| Volume | E101C |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - May 2018 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Towards ultra-high-speed cryogenic single-flux-quantum computing. / Ishida, Koki; Tanaka, Masamitsu; Ono, Takatsugu; Inoue, Koji.
In: IEICE Transactions on Electronics, Vol. E101C, No. 5, 05.2018, p. 359-369.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Towards ultra-high-speed cryogenic single-flux-quantum computing
AU - Ishida, Koki
AU - Tanaka, Masamitsu
AU - Ono, Takatsugu
AU - Inoue, Koji
PY - 2018/5
Y1 - 2018/5
N2 - CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.
AB - CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.
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U2 - 10.1587/transele.E101.C.359
DO - 10.1587/transele.E101.C.359
M3 - Article
AN - SCOPUS:85046434388
VL - E101C
SP - 359
EP - 369
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 5
ER -