Towards ultra-high-speed cryogenic single-flux-quantum computing

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.

Original languageEnglish
Pages (from-to)359-369
Number of pages11
JournalIEICE Transactions on Electronics
Issue number5
Publication statusPublished - May 2018

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


Dive into the research topics of 'Towards ultra-high-speed cryogenic single-flux-quantum computing'. Together they form a unique fingerprint.

Cite this