Towards ultra-high-speed cryogenic single-flux-quantum computing

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue

Research output: Contribution to journalArticle

Abstract

CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.

Original languageEnglish
Pages (from-to)359-369
Number of pages11
JournalIEICE Transactions on Electronics
VolumeE101C
Issue number5
DOIs
Publication statusPublished - May 2018

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Cryogenics
Fluxes
Microprocessor chips
Clocks
Pipelines
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Towards ultra-high-speed cryogenic single-flux-quantum computing. / Ishida, Koki; Tanaka, Masamitsu; Ono, Takatsugu; Inoue, Koji.

In: IEICE Transactions on Electronics, Vol. E101C, No. 5, 05.2018, p. 359-369.

Research output: Contribution to journalArticle

@article{438bf6bfe6e04e148ab1d51330f028dd,
title = "Towards ultra-high-speed cryogenic single-flux-quantum computing",
abstract = "CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.",
author = "Koki Ishida and Masamitsu Tanaka and Takatsugu Ono and Koji Inoue",
year = "2018",
month = "5",
doi = "10.1587/transele.E101.C.359",
language = "English",
volume = "E101C",
pages = "359--369",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "5",

}

TY - JOUR

T1 - Towards ultra-high-speed cryogenic single-flux-quantum computing

AU - Ishida, Koki

AU - Tanaka, Masamitsu

AU - Ono, Takatsugu

AU - Inoue, Koji

PY - 2018/5

Y1 - 2018/5

N2 - CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.

AB - CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.

UR - http://www.scopus.com/inward/record.url?scp=85046434388&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85046434388&partnerID=8YFLogxK

U2 - 10.1587/transele.E101.C.359

DO - 10.1587/transele.E101.C.359

M3 - Article

AN - SCOPUS:85046434388

VL - E101C

SP - 359

EP - 369

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 5

ER -