After a computer named "Deep Blue" defeated the world chess champion Garry Kasparov in 1997, researchers studying computer board games focused their attention on the game "Go." Go is known to be more difficult for computers to play than chess or shogi because (1) the search space for Go is much larger, (2) it is difficult to define an appropriate evaluation function of position, and (3) a position sometimes changes globally in just one move. Recently, a new method called Monte Carlo Go has been developed, which involves performing Monte Carlo simulations to evaluate a position. Monte Carlo Go increases the strength of the Computer-Go program. For Monte Carlo Go, the strength fully depends on the number of simulations. Several attempts were made to accelerate simulations, e.g., by the use of cluster systems and FPGAs. The cluster system yields good results, but it is a very expensive system. On the other hand, acceleration using an FPGA was not so easy because the usage of FPGA resources tends to be high. Previously, FPGA acceleration was feasible for smaller board such as a board with a 9 x 9 grid, while it was not feasible for the standard board with a 19 x 19 grid. In this paper, we propose triple line-based playout for Go (TLPG), a hardware algorithm for generating simulations using an FPGA. By reproducing global information redundantly, TLPG enables the generation of simulations only using local operations; this helps realize compact implementations of hardware logic, and thus, TLPG can handle both 9 x 9 and 19 x 19 grid Go boards. We implement TLPG on Xilinx Virtex-5 (XC5VFX70T-1FF1136) and evaluate it. TLPG can perform 40,649 playouts per second for a 9 x 9 grid Go board and 4,668 playouts per second for a 19 x 19 grid Go board.