Two-level processor scheduling for multiprogrammed NUMA multiprocessors

Akira Fukuda, Ryousuke Fujiki, Hisa aki Kai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Non-Uniform Memory Access multiprocessors have potential gains for achieving high performance. Theses machines are frequently used as computation servers with multiple parallel processes (we use this word instead of jobs) executing at the same time. In such environments, the efficiency of a parallel process can be significantly affected by the processor scheduling strategy. Two-level scheduling strategy, which is a kind of space-multiplexing scheduling strategy, is a promising one for large-scale multiprocessors. This paper describes the structure and interface of the two-level scheduling strategy. We also propose basic alternatives in this strategy: as alternatives of handling free processors, 1) Running-Process-First scheme and 2) Waiting-Process-First scheme; as alternatives of handling idle processors, 1) Idle-Processor-Hold scheme and 2) Idle-Processor-Release scheme. These alternatives are examined through simulation experiments.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society's International Computer Software & Applications Conference
Editors Anon
PublisherPubl by IEEE
Pages343-351
Number of pages9
ISBN (Print)0818644400
Publication statusPublished - 1993
EventProceedings of the 17th Annual International Computer Software & Applications Conference - COMPSAC 93 - Phoenix, AZ, USA
Duration: Nov 1 1993Nov 5 1993

Other

OtherProceedings of the 17th Annual International Computer Software & Applications Conference - COMPSAC 93
CityPhoenix, AZ, USA
Period11/1/9311/5/93

All Science Journal Classification (ASJC) codes

  • Software

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    Fukuda, A., Fujiki, R., & Kai, H. A. (1993). Two-level processor scheduling for multiprogrammed NUMA multiprocessors. In Anon (Ed.), Proceedings - IEEE Computer Society's International Computer Software & Applications Conference (pp. 343-351). Publ by IEEE.