Abstract
This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.
| Original language | English |
|---|---|
| Article number | 5395739 |
| Pages (from-to) | 299-312 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 29 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - Feb 1 2010 |
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All Science Journal Classification (ASJC) codes
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
Cite this
Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains. / Wang, Laung Terng; Wen, Xiaoqing; Wu, Shianling; Furukawa, Hiroshi; Chao, Hao Jan; Sheu, Boryau; Guo, Jianghao; Jone, Wen Ben.
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, 5395739, 01.02.2010, p. 299-312.Research output: Contribution to journal › Article
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TY - JOUR
T1 - Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains
AU - Wang, Laung Terng
AU - Wen, Xiaoqing
AU - Wu, Shianling
AU - Furukawa, Hiroshi
AU - Chao, Hao Jan
AU - Sheu, Boryau
AU - Guo, Jianghao
AU - Jone, Wen Ben
PY - 2010/2/1
Y1 - 2010/2/1
N2 - This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.
AB - This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.
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UR - http://www.scopus.com/inward/citedby.url?scp=76649120554&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2009.2035483
DO - 10.1109/TCAD.2009.2035483
M3 - Article
AN - SCOPUS:76649120554
VL - 29
SP - 299
EP - 312
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 2
M1 - 5395739
ER -