Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains

Laung Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao Jan Chao, Boryau Sheu, Jianghao Guo, Wen Ben Jone

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

Original languageEnglish
Article number5395739
Pages (from-to)299-312
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume29
Issue number2
DOIs
Publication statusPublished - Feb 1 2010

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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