TY - JOUR
T1 - Utilization of Multi-Resonant Defected Ground Structure Resonators in the Oscillator Feedback for Phase Noise Reduction of K-Band VCOs in 0.18-μ m CMOS Technology
AU - Jahan, Nusrat
AU - Baichuan, Chen
AU - Barakat, Adel
AU - Pokharel, Ramesh K.
N1 - Funding Information:
Manuscript received May 15, 2019; revised September 24, 2019; accepted January 2, 2020. Date of publication January 16, 2020; date of current version April 1, 2020. This work was supported in part by the Grant-in-Aid for Scientific Research (C) under Grant JP16K06301, in part by the Telecommunication Advancement Foundation, and in part by the VLSI Design and Education Center (VDEC), The University of Tokyo in collaboration with Cadence and Keysight Corporations. This article was recommended by Associate Editor E. Blokhina. (Corresponding author: Nusrat Jahan.) Nusrat Jahan is with the Department of Electrical and Electronic Engineering (EEE), Chittagong University of Engineering and Technology (CUET), Chittagong 4349, Bangladesh (e-mail: nusratjahan@cuet.ac.bd).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/4
Y1 - 2020/4
N2 - This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering (S) parameters of the resonators. In return, sharp S-parameters slope enhances the resonator loaded quality (Q) factor without compromising the unloaded Q-factor. In addition, the transmission pole can be realized near the second harmonic of the oscillation. This allocation of the transmission pole leads to the cancellation of this second harmonic and a further reduction of the phase noise. The proposed theory is verified by three different designs based on defected ground structure (DGS) resonators. These designs realized a low-band transmission pole before the parallel resonance, a high-band transmission pole after the parallel resonance, and dual-band transmission poles around the parallel resonance. First, each design is verified and compared to the others using circuit and electromagnetic simulations to establish the Q-factor improvement. Then, each of the resonators is utilized in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18-μ m CMOS technology and measured. The measurement results are in good agreement with the simulations, which confirm our claim about the proposed theory.
AB - This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering (S) parameters of the resonators. In return, sharp S-parameters slope enhances the resonator loaded quality (Q) factor without compromising the unloaded Q-factor. In addition, the transmission pole can be realized near the second harmonic of the oscillation. This allocation of the transmission pole leads to the cancellation of this second harmonic and a further reduction of the phase noise. The proposed theory is verified by three different designs based on defected ground structure (DGS) resonators. These designs realized a low-band transmission pole before the parallel resonance, a high-band transmission pole after the parallel resonance, and dual-band transmission poles around the parallel resonance. First, each design is verified and compared to the others using circuit and electromagnetic simulations to establish the Q-factor improvement. Then, each of the resonators is utilized in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18-μ m CMOS technology and measured. The measurement results are in good agreement with the simulations, which confirm our claim about the proposed theory.
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U2 - 10.1109/TCSI.2020.2965007
DO - 10.1109/TCSI.2020.2965007
M3 - Article
AN - SCOPUS:85082884311
SN - 1549-8328
VL - 67
SP - 1115
EP - 1125
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 4
M1 - 8961175
ER -