Ordered binary decision diagrams (OBDD’s), developed by Bryant, use restricted decision trees with shared subgraphs. The ordering of variables is fixed throughout an OBDD diagram. Using OBDD’s, 64-bit ALU circuits have been verified in a reasonable time. However, the size of an OBDD is very sensitive to variable ordering, especially for large circuits. This paper presents the results of experiments in variable ordering using an experimentally practical algorithm. The algorithm is basically a depth-first traversal through a circuit from the output to the inputs. With this algorithm, circuits having more than 3000 gates and more than 100 inputs can be expressed in reasonable CPU time and with practical memory requirements.
|Number of pages||7|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - Jan 1 1993|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering