VirtualScan: A new compressed scan technology for test cost reduction

Laung Terng Wang, Xiaoqing Wen, Hiroshi Furukawa, Fei Sheng Hsu, Shyh Horng Lin, Sen Wei Tsai, Khader S. Abdel-Hafez, Shianling Wu

Research output: Contribution to journalConference article

88 Citations (Scopus)

Abstract

This paper describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.

Original languageEnglish
Pages (from-to)916-925
Number of pages10
JournalProceedings - International Test Conference
Publication statusPublished - Dec 1 2004
EventProceedings - International Test Conference 2004 - Charlotte, NC, United States
Duration: Oct 26 2004Oct 28 2004

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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