VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.

Kazuo Seo, Hiroshi Fujita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A parameterized design methodology is one of the most effective methods of coping with the increasing design complexity of VLSI. However, the design cost of parameterized modules is very high. In order to reduce the burden on designers, a method based on inductive inference is introduced into the design process of parameterized modules. The authors present the layout-pattern extrapolator, which generates a parameterized module from some sample layout descriptions. By embedding the extrapolator in an interactive design environment, designers can easily design parameterized modules just by inputting a few sample layouts of that module.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages826-830
Number of pages5
ISBN (Print)0818605638
Publication statusPublished - 1984
Externally publishedYes

Fingerprint

Extrapolation
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Seo, K., & Fujita, H. (1984). VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. In Unknown Host Publication Title (pp. 826-830). IEEE.

VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. / Seo, Kazuo; Fujita, Hiroshi.

Unknown Host Publication Title. IEEE, 1984. p. 826-830.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seo, K & Fujita, H 1984, VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. in Unknown Host Publication Title. IEEE, pp. 826-830.
Seo K, Fujita H. VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. In Unknown Host Publication Title. IEEE. 1984. p. 826-830
Seo, Kazuo ; Fujita, Hiroshi. / VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION. Unknown Host Publication Title. IEEE, 1984. pp. 826-830
@inproceedings{5fa923e11d6e4ab0a86da5a3906cf943,
title = "VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.",
abstract = "A parameterized design methodology is one of the most effective methods of coping with the increasing design complexity of VLSI. However, the design cost of parameterized modules is very high. In order to reduce the burden on designers, a method based on inductive inference is introduced into the design process of parameterized modules. The authors present the layout-pattern extrapolator, which generates a parameterized module from some sample layout descriptions. By embedding the extrapolator in an interactive design environment, designers can easily design parameterized modules just by inputting a few sample layouts of that module.",
author = "Kazuo Seo and Hiroshi Fujita",
year = "1984",
language = "English",
isbn = "0818605638",
pages = "826--830",
booktitle = "Unknown Host Publication Title",
publisher = "IEEE",

}

TY - GEN

T1 - VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.

AU - Seo, Kazuo

AU - Fujita, Hiroshi

PY - 1984

Y1 - 1984

N2 - A parameterized design methodology is one of the most effective methods of coping with the increasing design complexity of VLSI. However, the design cost of parameterized modules is very high. In order to reduce the burden on designers, a method based on inductive inference is introduced into the design process of parameterized modules. The authors present the layout-pattern extrapolator, which generates a parameterized module from some sample layout descriptions. By embedding the extrapolator in an interactive design environment, designers can easily design parameterized modules just by inputting a few sample layouts of that module.

AB - A parameterized design methodology is one of the most effective methods of coping with the increasing design complexity of VLSI. However, the design cost of parameterized modules is very high. In order to reduce the burden on designers, a method based on inductive inference is introduced into the design process of parameterized modules. The authors present the layout-pattern extrapolator, which generates a parameterized module from some sample layout descriptions. By embedding the extrapolator in an interactive design environment, designers can easily design parameterized modules just by inputting a few sample layouts of that module.

UR - http://www.scopus.com/inward/record.url?scp=0021570280&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0021570280&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0818605638

SP - 826

EP - 830

BT - Unknown Host Publication Title

PB - IEEE

ER -