VLSI DESIGN USING LAYOUT-PATTERN EXTRAPOLATION.

A parameterized design methodology is one of the most effective methods of coping with the increasing design complexity of VLSI. However, the design cost of parameterized modules is very high. In order to reduce the burden on designers, a method based on inductive inference is introduced into the design process of parameterized modules. The authors present the layout-pattern extrapolator, which generates a parameterized module from some sample layout descriptions. By embedding the extrapolator in an interactive design environment, designers can easily design parameterized modules just by inputting a few sample layouts of that module.