Wafer-level compliant bump for 3D chip-stacking

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
Pages135-136
Number of pages2
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China
Duration: Apr 24 2006Apr 26 2006

Other

Other2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
CountryTaiwan, Province of China
CityHsinchu
Period4/24/064/26/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Watanabe, N., Kojima, T., & Asano, T. (2006). Wafer-level compliant bump for 3D chip-stacking. In 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers (pp. 135-136). [4016636] https://doi.org/10.1109/VTSA.2006.251100

Wafer-level compliant bump for 3D chip-stacking. / Watanabe, Naoya; Kojima, Takeaki; Asano, Tanemasa.

2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers. 2006. p. 135-136 4016636.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Watanabe, N, Kojima, T & Asano, T 2006, Wafer-level compliant bump for 3D chip-stacking. in 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers., 4016636, pp. 135-136, 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA, Hsinchu, Taiwan, Province of China, 4/24/06. https://doi.org/10.1109/VTSA.2006.251100
Watanabe N, Kojima T, Asano T. Wafer-level compliant bump for 3D chip-stacking. In 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers. 2006. p. 135-136. 4016636 https://doi.org/10.1109/VTSA.2006.251100
Watanabe, Naoya ; Kojima, Takeaki ; Asano, Tanemasa. / Wafer-level compliant bump for 3D chip-stacking. 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers. 2006. pp. 135-136
@inproceedings{fe006b8b81804be18f9018bef34e2fbd,
title = "Wafer-level compliant bump for 3D chip-stacking",
abstract = "We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.",
author = "Naoya Watanabe and Takeaki Kojima and Tanemasa Asano",
year = "2006",
doi = "10.1109/VTSA.2006.251100",
language = "English",
isbn = "142440181X",
pages = "135--136",
booktitle = "2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers",

}

TY - GEN

T1 - Wafer-level compliant bump for 3D chip-stacking

AU - Watanabe, Naoya

AU - Kojima, Takeaki

AU - Asano, Tanemasa

PY - 2006

Y1 - 2006

N2 - We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

AB - We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

UR - http://www.scopus.com/inward/record.url?scp=34250363151&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34250363151&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2006.251100

DO - 10.1109/VTSA.2006.251100

M3 - Conference contribution

AN - SCOPUS:34250363151

SN - 142440181X

SN - 9781424401819

SP - 135

EP - 136

BT - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers

ER -