Wafer-level compliant bump for 3D chip-stacking

Naoya Watanabe; Takeaki Kojima; Tanemasa Asano

doi:10.1109/VTSA.2006.251100

Wafer-level compliant bump for 3D chip-stacking

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

Integrated Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

Original language	English
Title of host publication	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
Pages	135-136
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2006.251100
Publication status	Published - 2006
Event	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China Duration: Apr 24 2006 → Apr 26 2006

Other

Other	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	4/24/06 → 4/26/06

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1109/VTSA.2006.251100

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Watanabe, N, Kojima, T & Asano, T 2006, Wafer-level compliant bump for 3D chip-stacking. in 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers., 4016636, pp. 135-136, 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA, Hsinchu, Taiwan, Province of China, 4/24/06. https://doi.org/10.1109/VTSA.2006.251100

@inproceedings{fe006b8b81804be18f9018bef34e2fbd,

title = "Wafer-level compliant bump for 3D chip-stacking",

abstract = "We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.",

author = "Naoya Watanabe and Takeaki Kojima and Tanemasa Asano",

year = "2006",

doi = "10.1109/VTSA.2006.251100",

language = "English",

isbn = "142440181X",

pages = "135--136",

booktitle = "2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA ; Conference date: 24-04-2006 Through 26-04-2006",

}

TY - GEN

T1 - Wafer-level compliant bump for 3D chip-stacking

AU - Watanabe, Naoya

AU - Kojima, Takeaki

AU - Asano, Tanemasa

PY - 2006

Y1 - 2006

N2 - We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

AB - We introduce wafer-level compliant bump for 3D chip-stacking. The inter-chip connection up to 10000 bump connections is demonstrated. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in the device even when the bump bonding is performed directly on the device.

UR - http://www.scopus.com/inward/record.url?scp=34250363151&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34250363151&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2006.251100

DO - 10.1109/VTSA.2006.251100

M3 - Conference contribution

AN - SCOPUS:34250363151

SN - 142440181X

SN - 9781424401819

SP - 135

EP - 136

BT - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA

Y2 - 24 April 2006 through 26 April 2006

ER -

Wafer-level compliant bump for 3D chip-stacking

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All Science Journal Classification (ASJC) codes

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