Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

Naoya Watanabe, Takeaki Kojima, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

We introduce the wafer-level compliant bump for chip stacking and 3-dimensional integration systems with high-density area bump interconnections. An inter-chip connection of up to 10,000 bump connections is demonstrated, where the bump size/pitch is 10 μm/20 μm. It is also demonstrated that the compliant bump is very effective in minimizing strain generated in a device even when the bump bonding is performed directly on the device.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages671-674
Number of pages4
Publication statusPublished - Dec 1 2005
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
Duration: Dec 5 2005Dec 7 2005

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2005
ISSN (Print)0163-1918

Other

OtherIEEE International Electron Devices Meeting, 2005 IEDM
CountryUnited States
CityWashington, DC, MD
Period12/5/0512/7/05

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Watanabe, N., Kojima, T., & Asano, T. (2005). Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest (pp. 671-674). [1609440] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005).