• 1880 引用
  • 19 h指数
1978 …2017
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1978 2017

2000
2 引用 (Scopus)

Flexible system LSI for embedded systems and its optimization techniques

Inoue, A., Ishihara, T. & Yasuura, H., 6 1 2000, : : Design Automation for Embedded Systems. 5, 2, p. 179-205 27 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Costs
Masks
Fabrication
Electric power utilization
2 引用 (Scopus)

Functional redundancy for dynamic exploitation of performance-energy consumption trade-offs

Goulart Ferreira, V. M. & Yasuura, H., 2000, Proceedings - 13th Symposium on Integrated Circuits and Systems Design. Institute of Electrical and Electronics Engineers Inc., p. 165-170 6 p. 876025

研究成果: 著書/レポートタイプへの貢献会議での発言

Redundancy
Energy utilization
Networks (circuits)
Electric power utilization
Systems analysis

One language or more? How can we design an SoC at a system level?

Imai, M., Smith, G., Schulz, S., Bartleson, K., Gajski, D. D., Rosenstiel, W., Flake, P. & Yasuura, H., 12 1 2000, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 653-654 2 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

System-on-chip

Synthesis of minimum-cost multilevel logic networks via genetic algorithm

Shackleford, B., Okushi, E., Yasuda, M., Koizuml, H., Seo, K. & Yasuura, H., 1 1 2000, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2528-2536 9 p.

研究成果: ジャーナルへの寄稿記事

Network Algorithms
Genetic algorithms
Genetic Algorithm
Synthesis
Logic
4 引用 (Scopus)

System LSI design methods for low power LSIs

Yasuura, H. & Ishihara, T., 1 1 2000, : : IEICE Transactions on Electronics. E83-C, 2, p. 143-152 10 p.

研究成果: ジャーナルへの寄稿記事

Systems analysis
1999
1 引用 (Scopus)
Embedded systems
Embedded Systems
Optimization Techniques
Data storage equipment
ROM

Educational results of hardware course with FPGAs

Sawada, S., Tomiyasu, H. & Yasuura, H., 3 1 1999, : : Research Reports on Information Science and Electrical Engineering of Kyushu University. 4, 1, p. 87-92 6 p.

研究成果: ジャーナルへの寄稿記事

Field programmable gate arrays (FPGA)
Students
Hardware
Microprocessor chips
Control facilities
59 引用 (Scopus)

Real-Time Task Scheduling for a Variable Voltage Processor

Okuma, T., Ishihara, T. & Yasuura, H., 11 1 1999, Proceedings of the 12th International Symposium on System Synthesis, ISSS 1999. IEEE Computer Society, (Proceedings of the International Symposium on System Synthesis; 巻数 Part F129194).

研究成果: 著書/レポートタイプへの貢献会議での発言

Scheduling
Electric potential
Program processors
Energy utilization
1998
2 引用 (Scopus)

A module generator of 2-level neuron MOS circuits

Ike, K., Hirose, K. & Yasuura, H., 1 1 1998, : : Computers and Electrical Engineering. 24, 1-2, p. 33-41 9 p.

研究成果: ジャーナルへの寄稿記事

Neurons
Networks (circuits)
MOSFET devices
Transistors
7 引用 (Scopus)

A test methodology for core-based system lsis

Sugihara, M., Date, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2640-2645 6 p.

研究成果: ジャーナルへの寄稿記事

Built-in self test
Methodology
Testing
Built-in Self-test
Combinatorial optimization
14 引用 (Scopus)

Embedded system design using soft-core processor and Valen-C

Yasuura, H., Tomiyama, H., Inoue, A. & Eko Fajar, N., 9 1998, : : Journal of Information Science and Engineering. 14, 3, p. 587-603 17 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Systems analysis
ROM
Random access storage
programming language

High-efficiency RF suppression circuit for fluorescent lamp inverters using charge pump and partial smoothing capacitors

Suzuki, F., Okino, K., Nishimura, Y., Yamazaki, H., Koizumi, H. & Yasuura, H., 1998, PESC Record - IEEE Annual Power Electronics Specialists Conference. Anon (版). 巻 2. p. 1733-1738 6 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

Fluorescent lamps
Capacitors
Pumps
Networks (circuits)
Electric lamps
14 引用 (Scopus)

Instruction encoding techniques for area minimization of instruction ROM

Okuma, T., Tomiyama, H., Inoue, A., Fajar, E. & Yasuura, H., 12 2 1998, Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998. Catthoor, F. (版). IEEE Computer Society, p. 125-130 6 p. (Proceedings of the International Symposium on System Synthesis; 巻数 Part F129250).

研究成果: 著書/レポートタイプへの貢献会議での発言

ROM
Embedded systems
Systems analysis
Data storage equipment
24 引用 (Scopus)

Instruction scheduling for power reduction in processor-based system design

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., 12 1 1998, : : Proceedings -Design, Automation and Test in Europe, DATE. p. 855-860 6 p., 655958.

研究成果: ジャーナルへの寄稿Conference article

Systems analysis
Scheduling
Scheduling algorithms
Data storage equipment
5 引用 (Scopus)

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2621-2629 9 p.

研究成果: ジャーナルへの寄稿記事

Instruction Scheduling
Power System
Cache
Chip
Capacitance
23 引用 (Scopus)

Language and compiler for optimizing datapath widths of embedded systems

Inoue, A., Tomiyama, H., Okuma, T., Kanbara, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2595-2604 10 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Embedded Systems
Compiler
ROM
Reusability
1 引用 (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., 1998, : : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 275-281 7 p.

研究成果: ジャーナルへの寄稿記事

Costs
High level synthesis
3 引用 (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2576-2584 9 p.

研究成果: ジャーナルへの寄稿記事

Manufacturing
High-level Synthesis
Module
Chip
Unit
48 引用 (Scopus)

Novel test methodology for core-based system LSIs and a testing time minimization problem

Sugihara, M., Date, H. & Yasuura, H., 12 1 1998, IEEE International Test Conference (TC). Anon (版). p. 465-472 8 p. (IEEE International Test Conference (TC)).

研究成果: 著書/レポートタイプへの貢献会議での発言

Built-in self test
Testing
Combinatorial optimization
5 引用 (Scopus)

Power-Pro: Programmable Power Management Architecture

Ishihara, T. & Yasuura, H., 1998, : : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 321-322 2 p.

研究成果: ジャーナルへの寄稿記事

Application programs
Clocks
Electric potential
Power management
8 引用 (Scopus)

Programmable power management architecture for power reduction

Ishihara, T. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Electronics. E81-C, 9, p. 1473-1479 7 p.

研究成果: ジャーナルへの寄稿記事

Clocks
Electric potential
Microprocessor chips
Electric power utilization
Power management
9 引用 (Scopus)

Program slicing on vhdl descriptions and its evaluation

Ichinoset, S., Iwaihara, M. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2585-2594 10 p.

研究成果: ジャーナルへの寄稿記事

Program Slicing
Computer hardware description languages
Evaluation
Slicing
Reuse
17 引用 (Scopus)

Soft-core processor architecture for embedded system design

Nurprasetyo, E. F., Inoue, A., Tomiyama, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Electronics. E81-C, 9, p. 1416-1422 7 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Systems analysis
Costs
Experiments
3 引用 (Scopus)

Statistical performance-driven module binding in high-level synthesis

Tomiyama, H., Inoue, A. & Yasuura, H., 12 2 1998, Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998. IEEE Computer Society, 巻 Part F129250. p. 66-71 6 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

Networks (circuits)
Clocks
Fabrication
High level synthesis
Costs
443 引用 (Scopus)

Voltage scheduling problem for dynamically variable voltage processors

Ishihara, T. & Yasuura, H., 1998, Proceedings of the International Symposium on Low Power Design. Anon (版). ACM, p. 197-202 6 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

Scheduling
Electric potential
Application programs
Linear programming
Energy utilization
142 引用 (Scopus)

Voltage scheduling problem for dynamically variable voltage processors

Ishihara, T. & Yasuura, H., 1998, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Anon (版). IEEE

研究成果: 著書/レポートタイプへの貢献会議での発言

Scheduling
Electric potential
Application programs
Linear programming
Energy utilization
1997
36 引用 (Scopus)

Code placement techniques for cache miss rate reduction

Tomiyama, H. & Yasuura, H., 1 1 1997, : : ACM Transactions on Design Automation of Electronic Systems. 2, 4, p. 410-429 20 p.

研究成果: ジャーナルへの寄稿記事

Cache memory
Embedded systems
Linear programming
Electric power utilization
Data storage equipment
6 引用 (Scopus)

Embedded system cost optimization via data path width adjustment

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., Inoue, A. & Yasuura, H., 1 1 1997, : : IEICE Transactions on Information and Systems. E80-D, 10, p. 974-981 8 p.

研究成果: ジャーナルへの寄稿記事

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware

HW/SW co-design environment for multi-media equipments development using inverse problem

Suzuki, F., Koizumi, H., Hiramine, M., Yamamoto, K., Yasuura, H. & Okino, K., 1997, Hardware/Software Codesign - Proceedings of the International Workshop. Anon (版). IEEE, p. 153-157 5 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

Inverse problems
Semiconductor materials
Television receivers
Numerical models
Hardware
16 引用 (Scopus)

Memory-CPU size optimization for embedded system designs

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., 1997, : : Proceedings - Design Automation Conference. p. 246-251 6 p.

研究成果: ジャーナルへの寄稿記事

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
1 引用 (Scopus)

Method for reconfigurable multimedia equipment development using inverse problem

Suzuki, F., Koizumi, H., Nishino, K. & Yasuura, H., 12 1 1997, p. 74-80. 7 p.

研究成果: 会議への寄与タイプ論文

Inverse problems
Television receivers
Reconfigurable architectures
Human engineering
Networks (circuits)

Rapid prototyping method for top-down design of system-on-chip devices using LPGAs

Suzuki, F., Koizumi, H., Seo, K., Yasuura, H., Hiramine, M., Okino, K. & Or-Bach, Z., 1997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, p. 9-18 10 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

Rapid prototyping
Lasers
Liquid crystal displays
Tuning
System-on-chip
1996
Plant layout
Digital circuits
Microprocessor chips
Logic Synthesis
1 引用 (Scopus)

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Ishihara, T. & Yasuura, H., 1996, International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, p. 117-120 4 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits

Ishihara, T. & Yasuura, H., 1996, IEEE Symposium on Low Power Electronics. Anon (版). IEEE, p. 117-120 4 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

VLSI circuits
Energy dissipation
Electric power utilization
Microprocessor chips
Clocks
11 引用 (Scopus)

Comparison of parallel multipliers with neuron MOS and CMOS technologies

Hirose, K. & Yasuura, H., 1996, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, p. 488-491 4 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

MOSFET devices
Neurons
Logic circuits
Adders
Networks (circuits)
1 引用 (Scopus)

On the computational power of binary decision diagram with redundant variables

Yamada, T. & Yasuura, H., 1 1 1996, : : Formal Methods in System Design. 8, 1, p. 65-89 25 p.

研究成果: ジャーナルへの寄稿記事

Binary decision diagrams
Decision Diagrams
Logarithmic
Polynomials
Binary

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., 3 11 1996, Proceedings of the 1996 European Conference on Design and Test, EDTC 1996. Association for Computing Machinery, Inc, p. 96-101 6 p. 494132. (Proceedings of the 1996 European Conference on Design and Test, EDTC 1996).

研究成果: 著書/レポートタイプへの貢献会議での発言

Embedded software
Linear programming
23 引用 (Scopus)

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., 1996, : : Proceedings of European Design and Test Conference. p. 96-101 6 p.

研究成果: ジャーナルへの寄稿記事

Embedded software
Linear programming
11 引用 (Scopus)

Satsuki: An integrated processor synthesis and compiler generation system

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., 1996, : : IEICE Transactions on Information and Systems. E79-D, 10, p. 1373-1381 9 p.

研究成果: ジャーナルへの寄稿記事

Computer peripheral equipment
Application programs
Computer hardware
Costs
Computer systems
7 引用 (Scopus)

Size-constrained code placement for cache miss rate reduction

Tomiyama, H. & Yasuura, H., 1996, : : Proceedings of the International Symposium on System Synthesis. p. 96-101 6 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Electric power utilization
1995
7 引用 (Scopus)

Proposal for a co-design method in control systems using combination of models

Koizumi, H., Seo, K., Suzuki, F., Ohtsuru, Y. & Yasuura, H., 3 1995, : : IEICE Transactions on Information and Systems. E78-D, 3, p. 237-247 11 p.

研究成果: ジャーナルへの寄稿記事

Control systems
Systems analysis
1994

Behavioral verification of cpus using functional information extraction

Ohmura, M., Tamaru, K. & Yasuura, H., 1 1 1994, : : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 77, 3, p. 52-61 10 p.

研究成果: ジャーナルへの寄稿記事

Program processors
Networks (circuits)
Logic circuits
Microprocessor chips
Computer aided design
1993
1 引用 (Scopus)

A micro-vectorprocessor Architecture - Performance Modeling and Benchmarking -

Hashimoto, T., Hironaka, T., Murakami, K. & Yasuura, H., 8 1 1993, Proceedings of the 7th International Conference on Supercomputing, ICS 1993. Association for Computing Machinery, p. 308-317 10 p. (Proceedings of the International Conference on Supercomputing; 巻数 Part F129670).

研究成果: 著書/レポートタイプへの貢献会議での発言

Benchmarking
Bandwidth
Data storage equipment
4 引用 (Scopus)

Bit-parallel block-parallel functional memory type parallel processor architecture

Kobayashi, K., Tamaru, K., Yasuura, H. & Onodera, H., 7 1993, : : IEICE Transactions on Electronics. E76-C, 7, p. 1151-1158 8 p.

研究成果: ジャーナルへの寄稿記事

Data storage equipment
Parallel architectures
Associative storage
18 引用 (Scopus)

COACH: a computer aided design tool for computer architects

Akaboshi, H. & Yasuura, H., 10 1993, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E76-A, 10, p. 1760-1769 10 p.

研究成果: ジャーナルへの寄稿記事

Computer-aided Design
Computer aided design
Compiler
Hardware
Layout
1992

A new VLSI algorithm for high throughput image filtering

Islam, F. F., Yasuura, H. & Tamaru, K., 1 1 1992, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., p. 2441-2444 4 p. 230523. (Proceedings - IEEE International Symposium on Circuits and Systems; 巻数 5).

研究成果: 著書/レポートタイプへの貢献会議での発言

Throughput
Masks
Pixels
Logic gates
1991

Functional information extraction from combinational circuits

Ohmura, M., Yasuura, H. & Tamaru, K., 1 1 1991, : : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 74, 11, p. 28-38 11 p.

研究成果: ジャーナルへの寄稿記事

Combinatorial circuits
Networks (circuits)
Binary decision diagrams
Logic design
Logic circuits

Locally computable coding for unary operations

Yasuura, H., 1 1 1991, Concurrency: Theory, Language, and Architecture - UK/Japan Workshop, Proceedings. Ito, T. & Yonezawa, A. (版). Springer Verlag, p. 312-323 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 491 LNCS).

研究成果: 著書/レポートタイプへの貢献会議での発言

Unary
State assignment
Redundancy
Coding
Parallel algorithms
1990
1 引用 (Scopus)

Extraction of functional information from combinational circuits

Ohmura, M., Yasuura, H. & Tamaru, K., 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 176-179 4 p.

研究成果: 著書/レポートタイプへの貢献会議での発言

Combinatorial circuits
Logic circuits
Networks (circuits)