• 1880 引用
  • 19 h指数
1978 …2017
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1978 2017

フィルター
記事
2012

A selective replacement method for timing-error-predicting flip-flops

Kunitake, Y., Sato, T., Yasuura, H. & Hayashida, T., 10 1 2012, : : Journal of Circuits, Systems and Computers. 21, 6, 1240013.

研究成果: ジャーナルへの寄稿記事

Flip flop circuits
Redundancy
Electric power utilization
Electric potential
Transistors
2011

Password based anonymous authentication with private information retrieval

Nakamura, T., Inenaga, S., Ikeda, D., Baba, K. & Yasuura, H., 4 1 2011, : : Journal of Digital Information Management. 9, 2, p. 72-78 7 p.

研究成果: ジャーナルへの寄稿記事

Information retrieval
information retrieval
Authentication
service provider
Private information
1 引用 (Scopus)

Short term cell-flipping technique for mitigating SNM degradation due to NBTI

Kunitake, Y., Sato, T. & Yasuura, H., 1 1 2011, : : IEICE Transactions on Electronics. E94-C, 4, p. 520-529 10 p.

研究成果: ジャーナルへの寄稿記事

Static random access storage
Transistors
Threshold voltage
Degradation
Recovery
2010
9 引用 (Scopus)

Code and data placement for embedded processors with scratchpad and cache memories

Ishitobi, Y., Ishihara, T. & Yasuura, H., 8 1 2010, : : Journal of Signal Processing Systems. 60, 2, p. 211-224 14 p.

研究成果: ジャーナルへの寄稿記事

Data Placement
Cache memory
Embedded Processor
Energy utilization
Energy Consumption
2009
1 引用 (Scopus)

An optimization technique for low-energy embedded memory systems

Matsumura, T., Ishihara, T. & Yasuura, H., 12 1 2009, : : IPSJ Transactions on System LSI Design Methodology. 2, p. 239-249 11 p.

研究成果: ジャーナルへの寄稿記事

Computer systems
Data storage equipment
Energy utilization
Memory architecture
Static random access storage
1 引用 (Scopus)

Enhancements of a circuit-level timing speculation technique and their evaluations using a co-simulation environment

Kunitake, Y., Mima, K., Sato, T. & Yasuura, H., 2009, : : IEICE Transactions on Electronics. E92-C, 4, p. 483-491 9 p.

研究成果: ジャーナルへの寄稿記事

Networks (circuits)
Delay circuits
Semiconductor materials

Single-cycle-accessible two-level caches and compilation technique for energy reducion

Yamaguchi, S., Ishitobi, Y., Ishihara, T. & Yasuura, H., 12 1 2009, : : IPSJ Transactions on System LSI Design Methodology. 2, p. 189-199 11 p.

研究成果: ジャーナルへの寄稿記事

Energy utilization
Data storage equipment
Degradation
Experiments
2008
1 引用 (Scopus)
Smart cards
Smart Card
One-way Hash Function
Function generators
Pseudorandom number Generator
1 引用 (Scopus)

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation

Goudarzi, M., Ishihara, T. & Yasuura, H., 12 1 2008, : : Microelectronics Journal. 39, 12, p. 1797-1808 12 p.

研究成果: ジャーナルへの寄稿記事

Static random access storage
Transistors
transistors
computer programs
life (durability)
2005

Bitwidth optimization for low power digital FIR filter design

Tarumi, K., Hyodo, A., Muroyama, M. & Yasuura, H., 1 1 2005, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 869-875 7 p.

研究成果: ジャーナルへの寄稿記事

FIR Filter
Digital Filter
Filter Design
FIR filters
Digital filters
2004
2 引用 (Scopus)

A power reduction scheme for data buses by dynamic detection of active bits

Muroyama, M., Hyodo, A., Okuma, T. & Yasuura, H., 4 2004, : : IEICE Transactions on Electronics. E87-C, 4, p. 598-605 8 p.

研究成果: ジャーナルへの寄稿記事

Electric power utilization
2003

Leakage Power Reduction for Battery-Operated Portable Systems

Cao, Y. & Yasuura, H., 12 2003, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3200-3203 4 p.

研究成果: ジャーナルへの寄稿記事

Leakage
Battery
Low-power Design
Parameter Design
Penalty
1 引用 (Scopus)

Pre-route power analysis techniques for SoC

Yamada, T., Sakamoto, T., Furuichi, S., Mukuno, M., Matsushita, Y. & Yasuura, H., 1 1 2003, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 3, p. 686-692 7 p.

研究成果: ジャーナルへの寄稿記事

Power Analysis
Transistors
Chip
Clocks
Capacitance
6 引用 (Scopus)

Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid

Sakai, A., Yamada, T., Matsushita, Y. & Yasuura, H., 10 1 2003, : : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11, 5, p. 951-954 4 p.

研究成果: ジャーナルへの寄稿記事

Crosstalk
Electric power utilization
Multilayers
Image processing
Networks (circuits)
1 引用 (Scopus)

Routing Methodology for Minimizing Crosstalk in SoC

Yamada, T., Sakai, A., Matsushita, Y. & Yasuura, H., 9 2003, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 9, p. 2347-2356 10 p.

研究成果: ジャーナルへの寄稿記事

Crosstalk
Routing
Chip
Methodology
Optimization Techniques

Routing methodology for minimizing interconnect energy dissipation

Sakai, A., Yamada, T., Matsushita, Y. & Yasuura, H., 2003, : : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 120-123 4 p.

研究成果: ジャーナルへの寄稿記事

Energy dissipation
Crosstalk
Image processing
Networks (circuits)
Costs
1 引用 (Scopus)

Variable Pipeline Depth Processor for Energy Efficient Systems

Hyodo, A., Muroyama, M. & Yasuura, H., 12 2003, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 2983-2990 8 p.

研究成果: ジャーナルへの寄稿記事

Energy Efficient
Pipelines
Energy Dissipation
Energy dissipation
Voltage
2002
5 引用 (Scopus)
Crosstalk
Wire
Telecommunication repeaters
SPICE
Switches

A proposal of secure information infrastructure based on PID

Hamasaki, Y. & Yasuura, H., 9 2002, : : Research Reports on Information Science and Electrical Engineering of Kyushu University. 7, 2, p. 139-148 10 p.

研究成果: ジャーナルへの寄稿記事

Memory organization for low-energy processor-based application-specific systems

Cao, Y. & Yasuura, H., 8 2002, : : IEICE Transactions on Electronics. E85-C, 8, p. 1616-1624 9 p.

研究成果: ジャーナルへの寄稿記事

Data storage equipment
Random access storage
Data transfer

Quality-driven design for video applications

Cao, Y. & Yasuura, H., 1 1 2002, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2568-2576 9 p.

研究成果: ジャーナルへの寄稿記事

MPEG-2
Optimization
Methodology
Design Methodology
Reuse

Special session: Security on SoC

Gebotys, C. & Yasuura, H., 2002, : : Proceedings of the International Symposium on System Synthesis. p. 192-194 3 p.

研究成果: ジャーナルへの寄稿記事

Cryptography
System-on-chip
Information systems
Energy utilization
Hardware
3 引用 (Scopus)
Computer science
Information technology
Information systems
Electric power utilization
2001
Built-in self test
Optimization
Bandwidth
Scheduling
Hardware
25 引用 (Scopus)

Software energy reduction techniques for variable-voltage processors

Okuma, T., Yasuura, H. & Ishihara, T., 3 1 2001, : : IEEE Design and Test of Computers. 18, 2, p. 31-41 11 p.

研究成果: ジャーナルへの寄稿記事

Electric potential
Real time systems
Scheduling
1 引用 (Scopus)
System Design
Design Methodology
Information Technology
Control Design
Semiconductors
2000
2 引用 (Scopus)

Flexible system LSI for embedded systems and its optimization techniques

Inoue, A., Ishihara, T. & Yasuura, H., 6 1 2000, : : Design Automation for Embedded Systems. 5, 2, p. 179-205 27 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Costs
Masks
Fabrication
Electric power utilization

Synthesis of minimum-cost multilevel logic networks via genetic algorithm

Shackleford, B., Okushi, E., Yasuda, M., Koizuml, H., Seo, K. & Yasuura, H., 1 1 2000, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2528-2536 9 p.

研究成果: ジャーナルへの寄稿記事

Network Algorithms
Genetic algorithms
Genetic Algorithm
Synthesis
Logic
4 引用 (Scopus)

System LSI design methods for low power LSIs

Yasuura, H. & Ishihara, T., 1 1 2000, : : IEICE Transactions on Electronics. E83-C, 2, p. 143-152 10 p.

研究成果: ジャーナルへの寄稿記事

Systems analysis
1999
1 引用 (Scopus)
Embedded systems
Embedded Systems
Optimization Techniques
Data storage equipment
ROM

Educational results of hardware course with FPGAs

Sawada, S., Tomiyasu, H. & Yasuura, H., 3 1 1999, : : Research Reports on Information Science and Electrical Engineering of Kyushu University. 4, 1, p. 87-92 6 p.

研究成果: ジャーナルへの寄稿記事

Field programmable gate arrays (FPGA)
Students
Hardware
Microprocessor chips
Control facilities
1998
2 引用 (Scopus)

A module generator of 2-level neuron MOS circuits

Ike, K., Hirose, K. & Yasuura, H., 1 1 1998, : : Computers and Electrical Engineering. 24, 1-2, p. 33-41 9 p.

研究成果: ジャーナルへの寄稿記事

Neurons
Networks (circuits)
MOSFET devices
Transistors
7 引用 (Scopus)

A test methodology for core-based system lsis

Sugihara, M., Date, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2640-2645 6 p.

研究成果: ジャーナルへの寄稿記事

Built-in self test
Methodology
Testing
Built-in Self-test
Combinatorial optimization
14 引用 (Scopus)

Embedded system design using soft-core processor and Valen-C

Yasuura, H., Tomiyama, H., Inoue, A. & Eko Fajar, N., 9 1998, : : Journal of Information Science and Engineering. 14, 3, p. 587-603 17 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Systems analysis
ROM
Random access storage
programming language
5 引用 (Scopus)

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2621-2629 9 p.

研究成果: ジャーナルへの寄稿記事

Instruction Scheduling
Power System
Cache
Chip
Capacitance
23 引用 (Scopus)

Language and compiler for optimizing datapath widths of embedded systems

Inoue, A., Tomiyama, H., Okuma, T., Kanbara, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2595-2604 10 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Embedded Systems
Compiler
ROM
Reusability
1 引用 (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., 1998, : : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 275-281 7 p.

研究成果: ジャーナルへの寄稿記事

Costs
High level synthesis
3 引用 (Scopus)

Module selection using manufacturing information

Tomiyama, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2576-2584 9 p.

研究成果: ジャーナルへの寄稿記事

Manufacturing
High-level Synthesis
Module
Chip
Unit
5 引用 (Scopus)

Power-Pro: Programmable Power Management Architecture

Ishihara, T. & Yasuura, H., 1998, : : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 321-322 2 p.

研究成果: ジャーナルへの寄稿記事

Application programs
Clocks
Electric potential
Power management
8 引用 (Scopus)

Programmable power management architecture for power reduction

Ishihara, T. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Electronics. E81-C, 9, p. 1473-1479 7 p.

研究成果: ジャーナルへの寄稿記事

Clocks
Electric potential
Microprocessor chips
Electric power utilization
Power management
9 引用 (Scopus)

Program slicing on vhdl descriptions and its evaluation

Ichinoset, S., Iwaihara, M. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2585-2594 10 p.

研究成果: ジャーナルへの寄稿記事

Program Slicing
Computer hardware description languages
Evaluation
Slicing
Reuse
17 引用 (Scopus)

Soft-core processor architecture for embedded system design

Nurprasetyo, E. F., Inoue, A., Tomiyama, H. & Yasuura, H., 1 1 1998, : : IEICE Transactions on Electronics. E81-C, 9, p. 1416-1422 7 p.

研究成果: ジャーナルへの寄稿記事

Embedded systems
Systems analysis
Costs
Experiments
1997
36 引用 (Scopus)

Code placement techniques for cache miss rate reduction

Tomiyama, H. & Yasuura, H., 1 1 1997, : : ACM Transactions on Design Automation of Electronic Systems. 2, 4, p. 410-429 20 p.

研究成果: ジャーナルへの寄稿記事

Cache memory
Embedded systems
Linear programming
Electric power utilization
Data storage equipment
6 引用 (Scopus)

Embedded system cost optimization via data path width adjustment

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., Inoue, A. & Yasuura, H., 1 1 1997, : : IEICE Transactions on Information and Systems. E80-D, 10, p. 974-981 8 p.

研究成果: ジャーナルへの寄稿記事

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
16 引用 (Scopus)

Memory-CPU size optimization for embedded system designs

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., 1997, : : Proceedings - Design Automation Conference. p. 246-251 6 p.

研究成果: ジャーナルへの寄稿記事

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
1996
Plant layout
Digital circuits
Microprocessor chips
Logic Synthesis
1 引用 (Scopus)

On the computational power of binary decision diagram with redundant variables

Yamada, T. & Yasuura, H., 1 1 1996, : : Formal Methods in System Design. 8, 1, p. 65-89 25 p.

研究成果: ジャーナルへの寄稿記事

Binary decision diagrams
Decision Diagrams
Logarithmic
Polynomials
Binary
23 引用 (Scopus)

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., 1996, : : Proceedings of European Design and Test Conference. p. 96-101 6 p.

研究成果: ジャーナルへの寄稿記事

Embedded software
Linear programming
11 引用 (Scopus)

Satsuki: An integrated processor synthesis and compiler generation system

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., 1996, : : IEICE Transactions on Information and Systems. E79-D, 10, p. 1373-1381 9 p.

研究成果: ジャーナルへの寄稿記事

Computer peripheral equipment
Application programs
Computer hardware
Costs
Computer systems