• 1887 引用
  • 19 h指数
1978 …2017
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1978 2017

フィルター
記事
1991

Functional information extraction from combinational circuits

Ohmura, M., Yasuura, H. & Tamaru, K., 1 1 1991, : : Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 74, 11, p. 28-38 11 p.

研究成果: ジャーナルへの寄稿記事

Combinatorial circuits
Networks (circuits)
Binary decision diagrams
Logic design
Logic circuits
1990
Random access storage
Data storage equipment
Parallel algorithms
Transistors
Computer systems
1989
2 引用 (Scopus)

Semantics of a hardware design language for Japanese standardization

Yasuura, H. & Ishiura, N., 1989, : : Proceedings - Design Automation Conference. p. 836-839 4 p.

研究成果: ジャーナルへの寄稿記事

Standardization
Semantics
Hardware
Linguistics
Simulators
1987
13 引用 (Scopus)

High-Speed Logic Simulation on Vector Processors

Ishiura, N., Yasuura, H. & Yajima, S., 1 1 1987, : : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 6, 3, p. 305-321 17 p.

研究成果: ジャーナルへの寄稿記事

Sequential circuits
Circuit simulation
Combinatorial circuits
Supercomputers
Processing

On high‐speed parallel algorithms using redundant coding

Yasuura, H., Takagi, N. & Yajima, S., 1 1 1987, : : Systems and Computers in Japan. 18, 12, p. 72-80 9 p.

研究成果: ジャーナルへの寄稿記事

Parallel algorithms
Parallel Algorithms
High Speed
Coding
Computability
1985
236 引用 (Scopus)

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Takagi, N., Yasuura, H. & Yajima, S., 1985, : : IEEE Transactions on Computers. C-34, 9, p. 789-796 8 p.

研究成果: ジャーナルへの寄稿記事

Trees (mathematics)
Multiplier
Multiplication
High Speed
Binary
1983
2 引用 (Scopus)

VLSI-ORIENTED HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDITION TREE.

Takagi, N., Yasuura, H. & Yajima, S., 1 1 1983, : : Systems, computers, controls. 14, 4, p. 19-28 10 p.

研究成果: ジャーナルへの寄稿記事

Binary trees
Adders
1982

ON THE AREA OF LOGIC CIRCUITS IN VLSI.

Yasuura, H. & Yajima, S., 7 1982, : : Systems, computers, controls. 13, 4, p. 101-110 10 p.

研究成果: ジャーナルへの寄稿記事

Logic circuits
Networks (circuits)
Logic design
Combinatorial circuits
VLSI circuits
30 引用 (Scopus)

The Parallel Enumeration Sorting Scheme for VLSI

Yasuura, H., Takagi, N. & Yajima, S., 1 1 1982, : : IEEE Transactions on Computers. C-31, 12, p. 1192-1201 10 p.

研究成果: ジャーナルへの寄稿記事

Sorting
Enumeration
Networks (circuits)
Cellular arrays
Data storage equipment
1981
1 引用 (Scopus)

Width and depth of combinational logic circuits

Yasuura, H., 1 1 1981, : : Information Processing Letters. 13, 4-5, p. 191-194 4 p.

研究成果: ジャーナルへの寄稿記事

Circuit Complexity
Combinatorial circuits
Logic circuits
Parallel Computation
Logic
1979

ON THE DEPTH OF COMBINATIONAL CIRCUITS REQUIRED TO COMPUTE SWITCHING FUNCTIONS.

Yasuura, H. & Yajima, S., 9 1979, : : Systems, computers, controls. 10, 5, p. 1-10 10 p.

研究成果: ジャーナルへの寄稿記事

Switching functions
Combinatorial circuits
Formal languages
Polynomials
1978

DESIGN OF ASYNCHRONOUS ARBITERS FROM THE STANDPOINT OF ASYNCHRONOUS SEQUENTIAL CIRCUIT THEORY.

Yasuura, H. & Yajima, S., 1 1 1978, : : Systems, computers, controls. 9, 6, p. 71-78 8 p.

研究成果: ジャーナルへの寄稿記事

Sequential circuits
Circuit theory