• 1905 引用
  • 19 h指数
1978 …2017

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

フィルター
Conference article
2009
1 引用 (Scopus)
2003

Routing methodology for minimizing interconnect energy dissipation

Sakai, A., Yamada, T., Matsushita, Y. & Yasuura, H., 2003, : : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 120-123 4 p.

研究成果: Contribution to journalConference article

2002

An accelerated datapath width optimization scheme for area reduction of embedded systems

Uddin, M. M., Cao, Y. & Yasuura, H., 2002, : : Proceedings of the International Symposium on System Synthesis. p. 32-37 6 p.

研究成果: Contribution to journalConference article

2 引用 (Scopus)

Data memory design considering effective bitwidth for low-energy embedded systems

Cao, Y., Tomiyama, H., Okuma, T. & Yasuura, H., 2002, : : Proceedings of the International Symposium on System Synthesis. p. 201-206 6 p.

研究成果: Contribution to journalConference article

25 引用 (Scopus)

Special session: Security on SoC

Gebotys, C. & Yasuura, H., 12 1 2002, : : Proceedings of the International Symposium on System Synthesis. p. 192-194 3 p.

研究成果: Contribution to journalConference article

2000

A bus delay reduction technique considering crosstalk

Hirose, K. & Yasuura, H., 2000, : : Proceedings -Design, Automation and Test in Europe, DATE. p. 441-445 5 p., 840308.

研究成果: Contribution to journalConference article

117 引用 (Scopus)

Analysis and minimization of test time in a combined BIST and external test approach

Sugihara, M., Date, H. & Yasuura, H., 2000, : : Proceedings -Design, Automation and Test in Europe, DATE. p. 134-140 7 p., 840029.

研究成果: Contribution to journalConference article

37 引用 (Scopus)

A power reduction technique with object code merging for application specific embedded processors

Ishihara, T. & Yasuura, H., 2000, : : Proceedings -Design, Automation and Test in Europe, DATE. p. 617-623 7 p., 840849.

研究成果: Contribution to journalConference article

30 引用 (Scopus)
1998

Instruction scheduling for power reduction in processor-based system design

Tomiyama, H., Ishihara, T., Inoue, A. & Yasuura, H., 1998, : : Proceedings -Design, Automation and Test in Europe, DATE. p. 855-860 6 p., 655958.

研究成果: Contribution to journalConference article

24 引用 (Scopus)
1997

Memory-CPU size optimization for embedded system designs

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H. & Yasuura, H., 1 1 1997, : : Proceedings - Design Automation Conference. p. 246-251 6 p.

研究成果: Contribution to journalConference article

16 引用 (Scopus)
1996

Optimal code placement of embedded software for instruction caches

Tomiyama, H. & Yasuura, H., 1 1 1996, : : Proceedings of European Design and Test Conference. p. 96-101 6 p.

研究成果: Contribution to journalConference article

23 引用 (Scopus)

Size-constrained code placement for cache miss rate reduction

Tomiyama, H. & Yasuura, H., 12 1 1996, : : Proceedings of the International Symposium on System Synthesis. p. 96-101 6 p.

研究成果: Contribution to journalConference article

7 引用 (Scopus)
1989

Semantics of a hardware design language for Japanese standardization

Yasuura, H. & Ishiura, N., 1989, : : Proceedings - Design Automation Conference. p. 836-839 4 p.

研究成果: Contribution to journalConference article

2 引用 (Scopus)
1982

An interactive simulation system for structured logic design - ISS

Sakai, T., Tsuchida, Y., Yasuura, H., Ooi, Y., Ono, Y., Kano, H., Kimura, S. & Yajima, S., 1 1 1982, : : Proceedings - Design Automation Conference. p. 747-754 8 p.

研究成果: Contribution to journalConference article

2 引用 (Scopus)