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Fingerprint Yusuke Matsunagaが取り組む研究トピックをご確認ください。これらのトピックラベルは、この人物の研究に基づいています。これらを共に使用することで、固有の認識が可能になります。

  • 3 同様のプロファイル
Binary decision diagrams Engineering & Materials Science
Networks (circuits) Engineering & Materials Science
Adders Engineering & Materials Science
Field programmable gate arrays (FPGA) Engineering & Materials Science
Combinatorial circuits Engineering & Materials Science
Throughput Engineering & Materials Science
Sequential circuits Engineering & Materials Science
Lithography Engineering & Materials Science

ネットワーク 最近の共同研究。丸をクリックして詳細を確認しましょう。

研究成果 1986 2019

An Efficient SAT-Attack Algorithm Against Logic Encryption

Matsunaga, Y. & Yoshimura, M., 7 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (版). Institute of Electrical and Electronics Engineers Inc., p. 44-47 4 p. 8854466. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

研究成果: 著書/レポートタイプへの貢献会議での発言

Cryptography
Program processors
Networks (circuits)
Experiments

An accelerating technique for SAT-based ATPG

Matsunaga, Y., 2 1 2017, : : IPSJ Transactions on System LSI Design Methodology. 10, p. 39-44 6 p.

研究成果: ジャーナルへの寄稿記事

Automatic test pattern generation
Program processors
Counterexample
Encoding
Refinement
Networks (circuits)
Compaction
Grouping
Fault
Compatibility
Efficient Algorithms
6 引用 (Scopus)

Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique

Matsunaga, Y., 3 11 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 255-260 6 p. 7059014. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

研究成果: 著書/レポートタイプへの貢献会議での発言

Field Programmable Gate Array
Program processors
Counterexample
Field programmable gate arrays (FPGA)
Encoding