A 10-Gb/s burst-mode CDR IC was fabricated in a 0.13-μm CMOS process for the high-speed packet-based networks of the future. The input amplifier employs a data-edge detection technique to enable instantaneous amplification from the first bit of each packet and AC-coupled input without a reset signal. The CDR core uses a gated VCO to enable instantaneous phase synchronization and clock extraction for burst data. Measurement results showed that the CDR IC operates at a data rate of 10Gb/s for burst and PRBS data with no error and recovers the clock and data in less than 5 UI (0.5ns) for burst data. This means that the burst-mode CDR IC is eight times faster than previous designs and can reduce a preamble time to less than one tenth the time for previous ones.
|寄稿の翻訳タイトル||A 10-Gb/s Burst-Mode CDR IC in 0.13-μm CMOS|
|ジャーナル||IEICE technical report|
|出版ステータス||出版済み - 5月 20 2005|