抄録
An UWB low noise amplifier exploiting current reused and linearization technique was designed using 0.18 um CMOS process. Post-distortion (PD) technique has applied to improve the linearity. The proposed design achieves +1dBm IIP3 measurement result, around 3dB noise figure, high and flat S21 of 15 dB, over a frequency range 3.1-10.6 GHz simulation results. The proposed design has consumed 18mW. The total chip area is 1.18mm2.
| 元の言語 | 英語 |
|---|---|
| ホスト出版物のタイトル | ICM 2016 - 28th International Conference on Microelectronics |
| 出版者 | Institute of Electrical and Electronics Engineers Inc. |
| ページ | 337-340 |
| ページ数 | 4 |
| ISBN（電子版） | 9781509057214 |
| DOI | |
| 出版物ステータス | 出版済み - 2 8 2017 |
| イベント | 28th International Conference on Microelectronics, ICM 2016 - Giza, エジプト 継続期間: 12 17 2016 → 12 20 2016 |
その他
| その他 | 28th International Conference on Microelectronics, ICM 2016 |
|---|---|
| 国 | エジプト |
| 市 | Giza |
| 期間 | 12/17/16 → 12/20/16 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
これを引用
+1dBm IIP3, low noise amplifier for ultra-wide band wireless applications. / Fahmy, Ghazal A.; Kanaya, Haruichi.
ICM 2016 - 28th International Conference on Microelectronics. Institute of Electrical and Electronics Engineers Inc., 2017. p. 337-340 7847884.研究成果: 著書/レポートタイプへの貢献 › 会議での発言
}
TY - GEN
T1 - +1dBm IIP3, low noise amplifier for ultra-wide band wireless applications
AU - Fahmy, Ghazal A.
AU - Kanaya, Haruichi
PY - 2017/2/8
Y1 - 2017/2/8
N2 - An UWB low noise amplifier exploiting current reused and linearization technique was designed using 0.18 um CMOS process. Post-distortion (PD) technique has applied to improve the linearity. The proposed design achieves +1dBm IIP3 measurement result, around 3dB noise figure, high and flat S21 of 15 dB, over a frequency range 3.1-10.6 GHz simulation results. The proposed design has consumed 18mW. The total chip area is 1.18mm2.
AB - An UWB low noise amplifier exploiting current reused and linearization technique was designed using 0.18 um CMOS process. Post-distortion (PD) technique has applied to improve the linearity. The proposed design achieves +1dBm IIP3 measurement result, around 3dB noise figure, high and flat S21 of 15 dB, over a frequency range 3.1-10.6 GHz simulation results. The proposed design has consumed 18mW. The total chip area is 1.18mm2.
UR - http://www.scopus.com/inward/record.url?scp=85014912031&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85014912031&partnerID=8YFLogxK
U2 - 10.1109/ICM.2016.7847884
DO - 10.1109/ICM.2016.7847884
M3 - Conference contribution
SP - 337
EP - 340
BT - ICM 2016 - 28th International Conference on Microelectronics
PB - Institute of Electrical and Electronics Engineers Inc.
ER -