29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

Ikki Nagaoka, Masamitsu Tanaka, Koji Inoue, Akira Fujimaki

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

3 被引用数 (Scopus)

抄録

A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

本文言語英語
ホスト出版物のタイトル2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ460-462
ページ数3
ISBN(電子版)9781538685310
DOI
出版ステータス出版済み - 3 6 2019
イベント2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, 米国
継続期間: 2 17 20192 21 2019

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2019-February
ISSN(印刷版)0193-6530

会議

会議2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Country米国
CitySan Francisco
Period2/17/192/21/19

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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