29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

Ikki Nagaoka, Masamitsu Tanaka, Inoue Koji, Akira Fujimaki

研究成果: 著書/レポートタイプへの貢献会議での発言

抄録

A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

元の言語英語
ホスト出版物のタイトル2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
出版者Institute of Electrical and Electronics Engineers Inc.
ページ460-462
ページ数3
ISBN(電子版)9781538685310
DOI
出版物ステータス出版済み - 3 6 2019
イベント2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, 米国
継続期間: 2 17 20192 21 2019

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2019-February
ISSN(印刷物)0193-6530

会議

会議2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
米国
San Francisco
期間2/17/192/21/19

Fingerprint

Fluxes
Superconducting materials
Clocks
Electric power utilization
Throughput
Testing

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Nagaoka, I., Tanaka, M., Koji, I., & Fujimaki, A. (2019). 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. : 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 (pp. 460-462). [8662351] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 巻数 2019-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2019.8662351

29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. / Nagaoka, Ikki; Tanaka, Masamitsu; Koji, Inoue; Fujimaki, Akira.

2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 460-462 8662351 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 巻 2019-February).

研究成果: 著書/レポートタイプへの貢献会議での発言

Nagaoka, I, Tanaka, M, Koji, I & Fujimaki, A 2019, 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. : 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019., 8662351, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 巻. 2019-February, Institute of Electrical and Electronics Engineers Inc., pp. 460-462, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019, San Francisco, 米国, 2/17/19. https://doi.org/10.1109/ISSCC.2019.8662351
Nagaoka I, Tanaka M, Koji I, Fujimaki A. 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. : 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 460-462. 8662351. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2019.8662351
Nagaoka, Ikki ; Tanaka, Masamitsu ; Koji, Inoue ; Fujimaki, Akira. / 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 460-462 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
@inproceedings{7fe218244ee54728965ab43e69806e68,
title = "29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic",
abstract = "A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.",
author = "Ikki Nagaoka and Masamitsu Tanaka and Inoue Koji and Akira Fujimaki",
year = "2019",
month = "3",
day = "6",
doi = "10.1109/ISSCC.2019.8662351",
language = "English",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "460--462",
booktitle = "2019 IEEE International Solid-State Circuits Conference, ISSCC 2019",
address = "United States",

}

TY - GEN

T1 - 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

AU - Nagaoka, Ikki

AU - Tanaka, Masamitsu

AU - Koji, Inoue

AU - Fujimaki, Akira

PY - 2019/3/6

Y1 - 2019/3/6

N2 - A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

AB - A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

UR - http://www.scopus.com/inward/record.url?scp=85063494903&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85063494903&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2019.8662351

DO - 10.1109/ISSCC.2019.8662351

M3 - Conference contribution

AN - SCOPUS:85063494903

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 460

EP - 462

BT - 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

ER -