TY - GEN
T1 - 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption
AU - Inoue, Koji
AU - Hashiguchi, Shinya
AU - Ueno, Shinya
AU - Fukumoto, Naoto
AU - Murakami, Kazuaki
PY - 2011/10/13
Y1 - 2011/10/13
N2 - This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.
AB - This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.
UR - http://www.scopus.com/inward/record.url?scp=80053649007&partnerID=8YFLogxK
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U2 - 10.1109/MWSCAS.2011.6026484
DO - 10.1109/MWSCAS.2011.6026484
M3 - Conference contribution
AN - SCOPUS:80053649007
SN - 9781612848570
T3 - Midwest Symposium on Circuits and Systems
BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Y2 - 7 August 2011 through 10 August 2011
ER -