3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

Koji Inoue, Shinya Hashiguchi, Shinya Ueno, Naoto Fukumoto, Kazuaki Murakami

研究成果: 著書/レポートタイプへの貢献 › 会議での発言

3 引用 (Scopus)

抄録

This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.

元の言語英語
ホスト出版物のタイトル54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOI
出版物ステータス出版済み - 10 13 2011
イベント54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, 大韓民国
継続期間: 8 7 2011 → 8 10 2011

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
ISSN（印刷物）1548-3746

その他

その他54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
国大韓民国
市Seoul
期間8/7/11 → 8/10/11

Fingerprint

Dynamic random access storage
Static random access storage
Electric power utilization
Application programs
Microprocessor chips
Computer systems
Degradation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Inoue, K., Hashiguchi, S., Ueno, S., Fukumoto, N., & Murakami, K. (2011). 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. ： 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026484] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026484

3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. / Inoue, Koji; Hashiguchi, Shinya; Ueno, Shinya; Fukumoto, Naoto; Murakami, Kazuaki.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026484 (Midwest Symposium on Circuits and Systems).

研究成果: 著書/レポートタイプへの貢献 › 会議での発言

Inoue, K, Hashiguchi, S, Ueno, S, Fukumoto, N & Murakami, K 2011, 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. ： 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026484, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, 大韓民国, 8/7/11. https://doi.org/10.1109/MWSCAS.2011.6026484
Inoue K, Hashiguchi S, Ueno S, Fukumoto N, Murakami K. 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. ： 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026484. (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026484
Inoue, Koji ; Hashiguchi, Shinya ; Ueno, Shinya ; Fukumoto, Naoto ; Murakami, Kazuaki. / 3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. (Midwest Symposium on Circuits and Systems).
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