3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. OmuraH. Ohashi, H. Iwai

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

抄録

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - Vce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

本文言語英語
ホスト出版物のタイトルProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
編集者Yajie Qin, Zhiliang Hong, Ting-Ao Tang
出版社IEEE Computer Society
ページ1137-1140
ページ数4
ISBN(電子版)9781509066247
DOI
出版ステータス出版済み - 7 1 2017
イベント12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, 中国
継続期間: 10 25 201710 28 2017

出版物シリーズ

名前Proceedings of International Conference on ASIC
2017-October
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

その他

その他12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
Country中国
CityGuiyang
Period10/25/1710/28/17

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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