3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)

K. Tsutsui; K. Kakushima; T. Hoshii; A. Nakajima; S. Nishizawa; H. Wakabayashi; I. Muneta; K. Sato; T. Matsudai; W. Saito; T. Saraya; K. Itou; M. Fukui; S. Suzuki; M. Kobayashi; T. Takakura; T. Hiramoto; A. Ogura; Y. Numasawa; I. Omura; H. Ohashi; H. Iwai

doi:10.1109/ASICON.2017.8252681

3D scaling for insulated gate bipolar transistors (IGBTs) with low V_ce(sat)

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. OmuraH. Ohashi, H. Iwai

研究成果: 書籍/レポートタイプへの寄稿 › 会議への寄与

抄録

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - V_ce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.

本文言語	英語
ホスト出版物のタイトル	Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
編集者	Yajie Qin, Zhiliang Hong, Ting-Ao Tang
出版社	IEEE Computer Society
ページ	1137-1140
ページ数	4
ISBN（電子版）	9781509066247
DOI	https://doi.org/10.1109/ASICON.2017.8252681
出版ステータス	出版済み - 7月 1 2017
イベント	12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, 中国継続期間: 10月 25 2017 → 10月 28 2017

出版物シリーズ

名前	Proceedings of International Conference on ASIC
巻	2017-October
ISSN（印刷版）	2162-7541
ISSN（電子版）	2162-755X

その他

その他	12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
国/地域	中国
City	Guiyang
Period	10/25/17 → 10/28/17

!!!All Science Journal Classification (ASJC) codes

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/ASICON.2017.8252681

他のファイルとリンク

引用スタイル

Tsutsui, K., Kakushima, K., Hoshii, T., Nakajima, A., Nishizawa, S., Wakabayashi, H., Muneta, I., Sato, K., Matsudai, T., Saito, W., Saraya, T., Itou, K., Fukui, M., Suzuki, S., Kobayashi, M., Takakura, T., Hiramoto, T., Ogura, A., Numasawa, Y., ... Iwai, H. (2017). 3D scaling for insulated gate bipolar transistors (IGBTs) with low V_ce(sat). In Y. Qin, Z. Hong, & T-A. Tang (Eds.), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (pp. 1137-1140). (Proceedings of International Conference on ASIC; Vol. 2017-October). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252681

3D scaling for insulated gate bipolar transistors (IGBTs) with low V_ce(sat). / Tsutsui, K.; Kakushima, K.; Hoshii, T. その他.
Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. ed. / Yajie Qin; Zhiliang Hong; Ting-Ao Tang. IEEE Computer Society, 2017. p. 1137-1140 (Proceedings of International Conference on ASIC; Vol. 2017-October).

研究成果: 書籍/レポートタイプへの寄稿 › 会議への寄与

Tsutsui, K, Kakushima, K, Hoshii, T, Nakajima, A, Nishizawa, S, Wakabayashi, H, Muneta, I, Sato, K, Matsudai, T, Saito, W, Saraya, T, Itou, K, Fukui, M, Suzuki, S, Kobayashi, M, Takakura, T, Hiramoto, T, Ogura, A, Numasawa, Y, Omura, I, Ohashi, H & Iwai, H 2017, 3D scaling for insulated gate bipolar transistors (IGBTs) with low V_ce(sat). in Y Qin, Z Hong & T-A Tang (eds), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Proceedings of International Conference on ASIC, vol. 2017-October, IEEE Computer Society, pp. 1137-1140, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, 中国, 10/25/17. https://doi.org/10.1109/ASICON.2017.8252681

Tsutsui K, Kakushima K, Hoshii T, Nakajima A, Nishizawa S, Wakabayashi H その他. 3D scaling for insulated gate bipolar transistors (IGBTs) with low V_ce(sat). In Qin Y, Hong Z, Tang T-A, editors, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society. 2017. p. 1137-1140. (Proceedings of International Conference on ASIC). doi: 10.1109/ASICON.2017.8252681

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abstract = "Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, - Vce(sat) reduction from 1.70 to 1.26 V - was experimentally confirmed for the 3D scaled IGBTs.",

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AU - Nishizawa, S.

AU - Wakabayashi, H.

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AU - Iwai, H.

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