抄録
A simple CMOS broadband power amplifier design with high linearity and good efficiency is proposed.The proposed power amplifier design employed stagger tuning technique that consist of two stages amplifier with different resonant frequencies to obtain a wider bandwidth from 0.9 to 3.5 GHz and low power consumption. To obtain high linearity self-biased circuit is employed at the first stage of amplifier. The measurement results indicated that the proposed design achieves average gain of 8.5 dB, an input return loss (S 11) less than -3 dB and output return loss (S 22) less than -5 dB. High linearity, that is, IIP3 of 13.4 dBm at 2 GHz, power added efficiency of 34% is obtained while consuming 24.4 mW power from 1.5 V supply voltage.
| 元の言語 | 英語 |
|---|---|
| ページ（範囲） | 2881-2884 |
| ページ数 | 4 |
| ジャーナル | Microwave and Optical Technology Letters |
| 巻 | 54 |
| 発行部数 | 12 |
| DOI | |
| 出版物ステータス | 出版済み - 12 1 2012 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Electrical and Electronic Engineering
これを引用
A 0.9-3.5 GHz high linearity, good efficiency CMOS broadband power amplifier using stagger tuning technique. / Sapawi, Rohana; Pokharel, Ramesh; Awang Mat, Dayang Azra; Kanaya, Haruichi; Yoshida, Keiji.
：: Microwave and Optical Technology Letters, 巻 54, 番号 12, 01.12.2012, p. 2881-2884.研究成果: ジャーナルへの寄稿 › 記事
}
TY - JOUR
T1 - A 0.9-3.5 GHz high linearity, good efficiency CMOS broadband power amplifier using stagger tuning technique
AU - Sapawi, Rohana
AU - Pokharel, Ramesh
AU - Awang Mat, Dayang Azra
AU - Kanaya, Haruichi
AU - Yoshida, Keiji
PY - 2012/12/1
Y1 - 2012/12/1
N2 - A simple CMOS broadband power amplifier design with high linearity and good efficiency is proposed.The proposed power amplifier design employed stagger tuning technique that consist of two stages amplifier with different resonant frequencies to obtain a wider bandwidth from 0.9 to 3.5 GHz and low power consumption. To obtain high linearity self-biased circuit is employed at the first stage of amplifier. The measurement results indicated that the proposed design achieves average gain of 8.5 dB, an input return loss (S 11) less than -3 dB and output return loss (S 22) less than -5 dB. High linearity, that is, IIP3 of 13.4 dBm at 2 GHz, power added efficiency of 34% is obtained while consuming 24.4 mW power from 1.5 V supply voltage.
AB - A simple CMOS broadband power amplifier design with high linearity and good efficiency is proposed.The proposed power amplifier design employed stagger tuning technique that consist of two stages amplifier with different resonant frequencies to obtain a wider bandwidth from 0.9 to 3.5 GHz and low power consumption. To obtain high linearity self-biased circuit is employed at the first stage of amplifier. The measurement results indicated that the proposed design achieves average gain of 8.5 dB, an input return loss (S 11) less than -3 dB and output return loss (S 22) less than -5 dB. High linearity, that is, IIP3 of 13.4 dBm at 2 GHz, power added efficiency of 34% is obtained while consuming 24.4 mW power from 1.5 V supply voltage.
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UR - http://www.scopus.com/inward/citedby.url?scp=84866636111&partnerID=8YFLogxK
U2 - 10.1002/mop.27212
DO - 10.1002/mop.27212
M3 - Article
VL - 54
SP - 2881
EP - 2884
JO - Microwave and Optical Technology Letters
JF - Microwave and Optical Technology Letters
SN - 0895-2477
IS - 12
ER -