A 10.3 Gb/s burst-mode CDR Using a ΔΣ DAC

Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

研究成果: ジャーナルへの寄稿学術誌査読

27 被引用数 (Scopus)

抄録

A burst-mode clock and data recovery circuit (CDR) for 10G-EPON systems is described. We propose a new architecture with a single gated voltage-controlled oscillator (GVCO), a digital frequency detector, and aDeltaSigma digital-to-analog converter (DAC). The single GVCO and detector reduce frequency error to less than 2 MHz. The \DeltaSigma DAC eliminates external devices. Moreover, the simulation results show the DAC is more tolerant to process, voltage, and temperature (PVT) variations than a conventional charge pump. We fabricated a test CDR with this architecture using the 0.25 μ m SiGe BiCMOS process. The measurement results show root-mean-square (rms) and total jitter of the recovered data of 2.4 and 14.7 ps, respectively, instantaneous locking in 1 bit, tolerance to a 160-bit sequence without transition in the data, and jitter tolerance of over 0.27 UIpp.

本文言語英語
論文番号4684637
ページ(範囲)2921-2928
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
43
12
DOI
出版ステータス出版済み - 12月 2008
外部発表はい

!!!All Science Journal Classification (ASJC) codes

  • 電子工学および電気工学

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