A 10.3125-Gbit/s SiGe BiCMOS burst-mode clock and data recovery circuit with 160-bit consecutive identical digit tolerance

Jun Terada, Kazuyoshi Nishimura, Minoru Togashi, Tomoaki Kawamura, Shunji Kimura, Yusuke Ohtomo

研究成果: Chapter in Book/Report/Conference proceedingConference contribution

2 被引用数 (Scopus)

抄録

A burst-mode clock and data recovery (CDR) circuit for 10 G-EPON OLT receivers is presented. The CDR employs a single-VCO architecutre, which increases consecutive identical digit (CID) tolerance. The developed CDR demonstrates 160-bit CID tolerance.

本文言語英語
ホスト出版物のタイトル2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9783800730421
DOI
出版ステータス出版済み - 2007
外部発表はい
イベント2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007 - Berlin, ドイツ
継続期間: 9 16 20079 20 2007

出版物シリーズ

名前2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007

その他

その他2007 33rd European Conference and Exhibition of Optical Communication, ECOC 2007
Countryドイツ
CityBerlin
Period9/16/079/20/07

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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