A 12 to 24GHz high efficiency fully integrated 0.18μm CMOS power amplifier

Hamed Mosalam, Ahmed Allam, Hongting Jia, Adel Abdelrahman, Takana Kaho, Ramesh Pokharel

研究成果: ジャーナルへの寄稿レター

1 引用 (Scopus)

抄録

This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.

元の言語英語
ジャーナルIEICE Electronics Express
13
発行部数14
DOI
出版物ステータス出版済み - 1 1 2016

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Group delay
power amplifiers
Power amplifiers
CMOS
power efficiency
frequency ranges
power gain
flatness
Millimeter waves
millimeter waves
Electric power utilization
Tuning
direct current
chips
tuning
methodology
broadband
Networks (circuits)
output

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

これを引用

A 12 to 24GHz high efficiency fully integrated 0.18μm CMOS power amplifier. / Mosalam, Hamed; Allam, Ahmed; Jia, Hongting; Abdelrahman, Adel; Kaho, Takana; Pokharel, Ramesh.

:: IEICE Electronics Express, 巻 13, 番号 14, 01.01.2016.

研究成果: ジャーナルへの寄稿レター

Mosalam, Hamed ; Allam, Ahmed ; Jia, Hongting ; Abdelrahman, Adel ; Kaho, Takana ; Pokharel, Ramesh. / A 12 to 24GHz high efficiency fully integrated 0.18μm CMOS power amplifier. :: IEICE Electronics Express. 2016 ; 巻 13, 番号 14.
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AB - This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.

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