TY - JOUR
T1 - A 12 to 24GHz high efficiency fully integrated 0.18μm CMOS power amplifier
AU - Mosalam, Hamed
AU - Allam, Ahmed
AU - Jia, Hongting
AU - Abdelrahman, Adel
AU - Kaho, Takana
AU - Pokharel, Ramesh
N1 - Funding Information:
The authors would like to thank the ministry of higher Education (MoHE)-mission department, and Egypt-Japan University of Science and Technology (E-JUST) for funding our work. In addition, a part of this work is supported by a Grant-in-Aid for Scientific Research (C) (Number: 16K06301), VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Keysight Technologies.
Publisher Copyright:
© IEICE 2016.
PY - 2016
Y1 - 2016
N2 - This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.
AB - This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.
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U2 - 10.1587/elex.13.20160551
DO - 10.1587/elex.13.20160551
M3 - Article
AN - SCOPUS:84979538995
VL - 13
JO - IEICE Electronics Express
JF - IEICE Electronics Express
SN - 1349-2543
IS - 14
M1 - 20160551
ER -