抄録
This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.
| 元の言語 | 英語 |
|---|---|
| ジャーナル | IEICE Electronics Express |
| 巻 | 13 |
| 発行部数 | 14 |
| DOI | |
| 出版物ステータス | 出版済み - 1 1 2016 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
これを引用
A 12 to 24GHz high efficiency fully integrated 0.18μm CMOS power amplifier. / Mosalam, Hamed; Allam, Ahmed; Jia, Hongting; Abdelrahman, Adel; Kaho, Takana; Pokharel, Ramesh.
：: IEICE Electronics Express, 巻 13, 番号 14, 01.01.2016.研究成果: ジャーナルへの寄稿 › レター
}
TY - JOUR
T1 - A 12 to 24GHz high efficiency fully integrated 0.18μm CMOS power amplifier
AU - Mosalam, Hamed
AU - Allam, Ahmed
AU - Jia, Hongting
AU - Abdelrahman, Adel
AU - Kaho, Takana
AU - Pokharel, Ramesh
PY - 2016/1/1
Y1 - 2016/1/1
N2 - This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.
AB - This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18μm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50mW.
UR - http://www.scopus.com/inward/record.url?scp=84979538995&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84979538995&partnerID=8YFLogxK
U2 - 10.1587/elex.13.20160551
DO - 10.1587/elex.13.20160551
M3 - Letter
AN - SCOPUS:84979538995
VL - 13
JO - IEICE Electronics Express
JF - IEICE Electronics Express
SN - 1349-2543
IS - 14
ER -